IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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Intel ® 82865GV GMCH BalloutThis page is intentionally left blank.230 Intel ® 82865G/82865GV GMCH Datasheet
Intel ® 82865GV GMCH BalloutTable 55. Intel ® 82865GVBall List bySignal NameSignal Name Ball #Table 55. Intel ® 82865GVBall List bySignal NameSignal Name Ball #Table 55. Intel ® 82865GVBall List bySignal NameSignal Name Ball #ADDID0R6DINV3#C15DVOC_HSYNCY4ADDID1P7DRDY#G24DVOC_VSYNCAA2ADDID2R3DREFCLKG4EXTTS#AP8ADDID3R5DVOB_BLANK#W5GCLKINH4ADDID4U9DVOBC_CLKINTW6GREENH6ADDID5U10DVOBC_INTR#P4GREEN#G5ADDID6U5DVOB_CLKAC6GVREFAD2ADDID7T7DVOB_CLK#AC5HA3#D26ADS#F27DVOBCRCOMPAC2HA4#D30BLUEH7DVOB_D0AE5HA5#L23BLUE#G6DVOB_D1AD5HA6#E29BNR#B28DVOB_D2AC9HA7#B32BPRI#B26DVOB_D3AA10HA8#K23BREQ0#B24DVOB_D4AB7HA9#C30BSEL0L13DVOB_D5AB11HA10#C31BSEL1L12DVOB_D6AA9HA11#J25CI_RCOMPAG2DVOB_D7Y7HA12#B31CI_SWINGAF2DVOB_D8AA5HA13#E30CI_VREFAF4DVOB_D9AA6HA14#B33CI0AK7DVOB_D10AA11HA15#J24CI1AH7DVOB_D11W10HA16#F25CI10AG6DVOB_FLDSTLW9HA17#D34CI2AD11DVOB_HSYNCAE6HA18#C32CI3AF7DVOB_VSYNCAC11HA19#F28CI4AD7DVOC_BLANK#Y2HA20#C34CI5AC10DVOC_CLKV4HA21#J27CI6AF8DVOC_CLK#V5HA22#G27CI7AG7DVOC_D0W2HA23#F29CI8AE9DVOC_D1Y5HA24#E28CI9AH9DVOC_D2V2HA25#H27CISTRFAJ6DVOC_D3W3HA26#K24CISTRSAJ5DVOC_D4U3HA27#E32CPURST#E8DVOC_D5U2HA28#F31DBSY#E27DVOC_D6T4HA29#G30DDCA_CLKF2DVOC_D7T2HA30#J26DDCA_DATAH3DVOC_D8R2HA31#G26DEFER#L21DVOC_D9T5HADSTB0#B30DINV0#C17DVOC_D10P5HADSTB1#D28DINV1#L17DVOC_D11P2HCLKNC7DINV2#L14DVOC_FLDSTLM2HCLKPB7Intel ® 82865G/82865GV GMCH Datasheet 231
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Intel ® 865G/865GV ChipsetDatashee
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Contents1 Introduction.............
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3.8 PCI-to-CSA Bridge Registers (De
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5.5.3 Synchronous Display .........
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Tables1 General Terminology .......
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Introduction1.4 Intel ® 82865G GMC
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Introduction1.4.7 Display Interface
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Signal Description2.1 Host Interfac
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Signal DescriptionSignal Name Type
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Signal Description2.2.2 DDR SDRAM C
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Signal Description2.5 AGP Interface
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Signal Description2.5.4 AGP Strobes
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Signal DescriptionSignal Name Type
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Signal Description2.5.7 Intel ® DV
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Signal Description2.7 Clocks, Reset
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Signal Description2.10 GMCH Sequenc
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Signal Description2.12 Full and War
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Register DescriptionTermReservedReg
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Register Description3.3 Routing Con
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Register DescriptionIf the Bus Numb
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Register Description3.4.2 CONFIG_DA
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Register DescriptionTable 6.DRAM Co
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Register Description3.5.3 PCICMD—
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Register Description3.5.5 RID—Rev
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Register Description3.5.10 APBASE
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Register Description3.5.14 AGPM—A
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Register DescriptionNotes on Pre-Al
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Register Description3.5.17 FPLLCONT
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Register DescriptionAs an example,
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Register Description3.5.20 SMRAM—
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Register Description3.5.22 ACAPID
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Register Description3.5.24 AGPCMD
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Register Description3.5.26 APSIZE
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Register Description3.5.29 LPTT—A
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Register Description3.5.31 GMCHCFG
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Register Description3.5.32 ERRSTS
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Register Description3.5.34 SKPD—S
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Register Description3.6.1 VID1—Ve
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Register Description3.6.4 PCISTS1
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Register Description3.6.8 MLT1—Ma
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Register Description3.6.14 IOBASE1
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Register Description3.6.17 MBASE1
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Register Description3.6.22 ERRCMD1
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Register Description3.7.6 CC—Clas
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Register Description3.7.11 MMADR—
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Register Description3.7.16 CAPPOINT
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Register Description3.7.22 PMCAP—
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Register Description3.8 PCI-to-CSA
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Register Description3.8.3 PCICMD3
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Register Description3.8.5 RID3—Re
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Register Description3.8.11 SBUSN3
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Register Description3.8.15 SSTS3—
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Register Description3.8.17 MLIMIT3
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Register Description3.8.20 BCTRL3
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Register Description3.9 Overflow Co
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Register Description3.9.4 PCISTS6
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Register Description3.9.9 BAR6—Me
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Register DescriptionThe remaining 7
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Register Description3.10.3 DRT—DR
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Register DescriptionBit6:4Descripti
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System Address MapSystem Address Ma
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System Address Map4.2 Compatibility
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System Address Map4.3 Extended Memo
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System Address MapPCI Memory Addres
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Functional DescriptionFunctional De
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Functional Description5.2 System Me
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Functional Description5.2.2.1 Dynam
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Functional DescriptionTable 21. DRA
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Functional DescriptionTable 23. DRA
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Functional Description5.2.6 Configu
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Functional Description5.3.1 GMCH AG
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Functional Descriptiondown controll
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Functional Description5.3.6 Support
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Functional Description5.4.1 3D Engi
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Functional DescriptionTexture Forma
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Functional DescriptionTexture Map B
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Functional DescriptionDepth BufferT
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Functional Description5.4.3 Video E
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Functional Description5.4.5 PipesSc
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Functional DescriptionIntegrated RA
Page 179 and 180: Functional DescriptionDirect YUV fr
Page 181 and 182: Functional Description• System—
Page 183 and 184: Functional Description5.8 ClockingT
Page 185 and 186: Electrical CharacteristicsElectrica
Page 187 and 188: Electrical CharacteristicsTable 36.
Page 189 and 190: Electrical Characteristics6.5 DC Pa
Page 195 and 196: Electrical Characteristics6.6.3 DAC
Page 197 and 198: Ballout and Package InformationBall
Page 199 and 200: Ballout and Package InformationFigu
Page 201 and 202: Ballout and Package InformationTabl
Page 209 and 210: Ballout and Package Information7.2
Page 211 and 212: TestabilityTestability 8In the GMCH
Page 213 and 214: Testability8.2 XOR Chain Definition
Page 215 and 216: TestabilityTable 45. XOR Chain 1 (3
Page 221 and 222: Intel ® 82865GV GMCHIntel ® 82865
Page 223 and 224: Intel ® 82865GV GMCH9.3 Intel ® 8
Page 225 and 226: Intel ® 82865GV GMCHGMCHCFG—GMCH
Page 227 and 228: Intel ® 82865GV GMCH BalloutIntel
Page 229: Intel ® 82865GV GMCH BalloutFigure
Page 233 and 234: Intel ® 82865GV GMCH BalloutTable
Page 241 and 242: Intel ® 82865GV GMCH TestabilityIn
Page 243 and 244: Intel ® 82865GV GMCH Testability11
Page 245 and 246: Intel ® 82865GV GMCH TestabilityTa
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IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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