Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.8.18 PMBASE3—Prefetchable Memory Base Address Register(Device 3)Address Offset:Default Value:Access:Size:24−25hFFF0hR/W, RO16 bitsThis register controls the processor-to-CSA prefetchable memory accesses routing based on thefollowing formula:PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMITThe upper 12 bits of the register are read/write and correspond to the upper 12 address bitsA[31:20] of the 32-bit address. The bottom four bits of this register are read only and return 0swhen read. This register must be initialized by the configuration software. For the purpose ofaddress decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memoryaddress range will be aligned to a 1-MB boundary.BitDescription15:4Prefetchable Memory Address Base (PMBASE)—R/W. This field corresponds to A[31:20] of thelower limit of the address range passed by bridge Device 3 across CSA.3:0 Reserved.3.8.19 PMLIMIT3—Prefetchable Memory Limit Address Register(Device 3)Address Offset:Default Value:Access:Size:26−27h0000hR/W, RO16 bitsThis register controls the processor to CSA prefetchable memory accesses routing based on thefollowing formula:PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMITThe upper 12 bits of the register are read/write and correspond to the upper 12 address bitsA[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return 0s whenread. This register must be initialized by the configuration software. For the purpose of addressdecode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memoryaddress range will be at the top of a 1-MB aligned memory block. Note that prefetchable memoryrange is supported to allow segregation by the configuration software between the memory rangesthat must be defined as UC and the ones that can be designated as a USWC (i.e., prefetchable) fromthe processor perspective.BitDescription15:4Prefetchable Memory Address Limit (PMLIMIT)—R/W. This field corresponds to A[31:20] of theupper limit of the address range passed by bridge Device 3 across CSA.3:0 Reserved.124 Intel ® 82865G/82865GV GMCH Datasheet