Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.10 Device 6 Memory-Mapped I/O Register SpaceThe DRAM timing and delay registers are located in the memory-mapped register (MMR) space ofDevice 6. Table 14 provides the register address map for this set of registers.Note:All accesses to these memory-mapped registers must be made as a single DWord (4 bytes) or less.Access must be aligned on a natural boundary.Table 14. Device 6 Memory-Mapped I/O Register Address MapByteAddressOffsetRegisterSymbolRegister Name Default Value Access0000h DRB0 DRAM Row 0 Boundary 01h RW0001h DRB1 DRAM Row 1 Boundary 01h RW0002h DRB2 DRAM Row 2 Boundary 01h RW0003h DRB3 DRAM Row 3 Boundary 01h RW0004h DRB4 DRAM Row 4 Boundary 01h RW0005h DRB5 DRAM Row 5 Boundary 01h RW0006h DRB6 DRAM Row 6 Boundary 01h RW0007h DRB7 DRAM Row 7 Boundary 01h RW0008–000Bh — Intel Reserved — —0010h DRA0,1 DRAM Row 0,1 Attribute 00h RW0011h DRA2,3 DRAM Row 2,3 Attribute 00h RW0012h DRA4,5 DRAM Row 4,5 Attribute 00h RW0013h DRA6,7 DRAM Row 6,7 Attribute 00h RW0014–005Fh — Intel Reserved — —0060–0063h DRT DRAM Timing 0000 0000h RW0064–0067h — Intel Reserved — —0068–006Bh DRC DRAM Controller Mode 0001 0001h RW006C–FFFFh — Intel Reserved — —3.10.1 DRB[0:7]—DRAM Row Boundary Register(Device 6, MMR)Address Offset:Default Value:Access:Size:0000h–0007h (DRB0–DRB7)00hR/W8 bits each registerThe DRAM row Boundary registers define the upper boundary address of each DRAM row. Eachrow has its own single-byte DRB register. The granularity of these registers is 64 MB. Forexample, a value of 1 in DRB0 indicates that 64 MB of DRAM has been populated in the first row.When in either of the two dual-channel modes, the granularity of these registers is still 64 MB. Inthis case, the lowest order bit in each register is always programmed to 0 yielding a minimumgranularity of 128 MB. Bit 7 of each of these registers is reserved and must be programmed to 0.132 Intel ® 82865G/82865GV GMCH Datasheet