Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Functional DescriptionTable 26 is only a subset of the defined SPD bytes on the DIMMs. These bytes collectively provideenough data for programming the GMCH SDRAM registers.5.2.7 Memory Thermal ManagementThe GMCH provides a thermal management method that selectively reduces reads and writes toDRAM when the access rate crosses the allowed thermal threshold.Read and write thermal management operate independently, and have their own 64-bit register tocontrol operation. Memory reads typically causes power dissipation in the DRAM chips whilememory writes typically causes power dissipation in the GMCH.5.2.7.1 Determining When to Thermal ManageThermal management may be enabled by one of two mechanisms:• Software forcing throttling via the SRT (SWT) bit.• Counter Mechanism.5.3 Accelerated Graphics Port (AGP)The GMCH supports AGP 3.0 with limited AGP 2.0 compatibility. The electrical characteristicsare supported for AGP 3.0 (0.8 V swing) and the AGP 2.0 (1.5 V swing). The GMCH may beoperated in 1X and 4X for AGP 2.0 mode at 1.5 V; 3.3 V electrical characteristics are notsupported.The GMCH has a 32 deep AGP request queue. The GMCH integrates two fully-associative10 entry Translation Look-aside Buffer. This 20 entry buffer is used for both reads and writes.The GMCH multiplexes an AGP interface with two DVO ports. When an external AGP device isutilized, the multiplexed DVO ports are not available as the GMCH’s IGD will be disabled. Formore information on the multiplexed DVO interface, see Section 5.5.2.See the AGP Revision 3.0 specification for additional details about the AGP interface.158 Intel ® 82865G/82865GV GMCH Datasheet