IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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Electrical CharacteristicsTable 37. DC Operating Characteristics (Sheet 2 of 2)Signal Name Parameter Min Nom Max UnitHDVREF 2 Host Reference Voltage 0.63 x Vsh_min – 2% 0.63 x Vsh0.63 x Vsh_max+ 2%VHDSWING/HASWINGHost CompensationReference Voltage1/4 x VTT_min – 2% 1/4 x VTT1/4 x VTT_max+ 2%VSMXRCOMPVOL 3 /SMYRCOMPVOLSMXRCOMPVOH 3 /SMYRCOMPVOHDDR RCOMP VOLVCC_DDR_min *(1/4.112) – 2%VCC_DDR *(1/4.112)VCC_DDR_max *(1/4.112) + 2%VDDR RCOMP VOHVCC_DDR_min *(3.112/4.112) - 2%VCC_DDR *(3.112/4.112)VCC_DDR_max *(3.112/4.112) + 2%VSMVREFDDR Reference Voltage0.49 xVCC_DDR_min0.5 x VCC_DDR0.51 xVCC_DDR_maxVNOTES:1. Refer to the Intel ® Pentium ® 4 Processor with 512-KB L2 Cache on 0.13 Micron Process Datasheet VCCvalues used to calculate Vsh. For values pertaining to the Pentium 4 processor on 90 nm process, contactyour Intel field representative.2. HDVREF is generically referred to as GTLREF throughout the rest of this chapter.3. SMXRCOMPVOL/SMYRCOMPVOL and SMXRCOMPVOH/SMYRCOMPVOH have maximum input leakagecurrent of 1 mA.4. Measured at receiver pad.5. Standard 50 Ω load to ground.6. HI_REF and HI_SWING are derived from VCC (nominal VCC = 1.5 V) that is the nominal core voltage for theGMCH. Voltage supply tolerance for a particular interface driver voltage must be within a 5% range ofnominal.7. Nominal value of HI_REF is 0.350 V. The specification is at nominal VCC. Note that HI_REF varies linearlywith VCC; thus, VCC variation (± 5%) must be accounted for in the HI_REF specification in addition to the 2%variation of HI_REF in the table.8. Nominal value of HI_SWING is 0.800 V. The specification is at nominal VCC. Note that HI_SWING varieslinearly with VCC; thus, VCC variation (± 5%) must be accounted for in the HI_SWING specification inaddition to the 2% variation of HI_SWING in the table.9. CI_REF and CI_SWING are derived from VCC (nominal VCC = 1.5 V) that is the nominal core voltage for theGMCH. Voltage supply tolerance for a particular interface driver voltage must be within a 5% range ofnominal.10.Nominal value of CI_VREF is 0.350 V. The specification is at nominal VCC. Note that CI_VREF varieslinearly with VCC; thus, VCC variation (± 5%) must be accounted for in the CI_VREF specification in additionto the 2% variation of CI_REF in the table.11.Nominal value of CI_SWING is 0.800 V. The specification is at nominal VCC. Note that CI_SWING varieslinearly with VCC; thus, VCC variation (± 5%) must be accounted for in the CI_SWING specification inaddition to the 2% variation of CI_SWING in the table.12.For AC noise components >20 MHz, the maximum allowable noise component at the GMCH is ±180 mV atVCC_nom, +180/-105 mV at VCC_min, and +105/-180 mV at VCC_max. For AC noise components
Electrical CharacteristicsTable 38. DC Characteristics (Sheet 1 of 3)SymbolSignalGroupParameter Min Nom Max Unit Notes1.5 V AGP 2.0 (1.5 V signaling) and DVO Interface 6V IL_AGPV IH_AGPV OL_AGPV OH_AGPI OL_AGPI OH_AGPI LEAK_AGPC IN_AGP(a,b,r)(a,b,r)(a,c,s)(a,c,s)(a,c,s)(a,c,s)(a,b,r)(a,b,r)AGP/DVO Input LowVoltageAGP/DVO Input HighVoltageAGP/DVO Output LowVoltageAGP/DVO Output HighVoltageAGP/DVO Output LowCurrentAGP/DVO Output HighCurrentAGP/DVO Input LeakageCurrentAGP/DVO InputCapacitance1.5 V AGP 3.0 (0.8 V signaling) and DVO Interface 6–0.5 AGP_VREF – 0.15 VAGP_VREF + 0.15 VCC_AGP + 0.5 V0.225 V1.275 V–4.7 mA6.65 mA @ 0.1* VCC_AGP±25 µA@ 0.85*VCC_AGP0
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Intel ® 865G/865GV ChipsetDatashee
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Contents1 Introduction.............
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3.8 PCI-to-CSA Bridge Registers (De
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5.5.3 Synchronous Display .........
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Tables1 General Terminology .......
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Introduction1.4 Intel ® 82865G GMC
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Introduction1.4.7 Display Interface
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Signal Description2.1 Host Interfac
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Signal DescriptionSignal Name Type
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Signal Description2.2.2 DDR SDRAM C
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Signal Description2.5 AGP Interface
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Signal Description2.5.4 AGP Strobes
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Signal DescriptionSignal Name Type
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Signal Description2.5.7 Intel ® DV
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Signal Description2.7 Clocks, Reset
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Signal Description2.10 GMCH Sequenc
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Signal Description2.12 Full and War
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Register DescriptionTermReservedReg
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Register Description3.3 Routing Con
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Register DescriptionIf the Bus Numb
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Register Description3.4.2 CONFIG_DA
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Register DescriptionTable 6.DRAM Co
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Register Description3.5.3 PCICMD—
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Register Description3.5.5 RID—Rev
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Register Description3.5.10 APBASE
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Register Description3.5.14 AGPM—A
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Register DescriptionNotes on Pre-Al
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Register Description3.5.17 FPLLCONT
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Register DescriptionAs an example,
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Register Description3.5.20 SMRAM—
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Register Description3.5.22 ACAPID
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Register Description3.5.24 AGPCMD
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Register Description3.5.26 APSIZE
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Register Description3.5.29 LPTT—A
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Register Description3.5.31 GMCHCFG
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Register Description3.5.32 ERRSTS
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Register Description3.5.34 SKPD—S
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Register Description3.6.1 VID1—Ve
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Register Description3.6.4 PCISTS1
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Register Description3.6.8 MLT1—Ma
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Register Description3.6.14 IOBASE1
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Register Description3.6.17 MBASE1
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Register Description3.6.22 ERRCMD1
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Register Description3.7.6 CC—Clas
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Register Description3.7.11 MMADR—
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Register Description3.7.16 CAPPOINT
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Register Description3.7.22 PMCAP—
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Register Description3.8 PCI-to-CSA
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Register Description3.8.3 PCICMD3
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Register Description3.8.5 RID3—Re
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Register Description3.8.11 SBUSN3
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Register Description3.8.15 SSTS3—
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Register Description3.8.17 MLIMIT3
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Register Description3.8.20 BCTRL3
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Register Description3.9 Overflow Co
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Register Description3.9.4 PCISTS6
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Register Description3.9.9 BAR6—Me
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Register DescriptionThe remaining 7
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Register Description3.10.3 DRT—DR
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Register DescriptionBit6:4Descripti
Page 139 and 140: System Address MapSystem Address Ma
Page 141 and 142: System Address Map4.2 Compatibility
Page 143 and 144: System Address Map4.3 Extended Memo
Page 145 and 146: System Address MapPCI Memory Addres
Page 147 and 148: Functional DescriptionFunctional De
Page 149 and 150: Functional Description5.2 System Me
Page 151 and 152: Functional Description5.2.2.1 Dynam
Page 153 and 154: Functional DescriptionTable 21. DRA
Page 155 and 156: Functional DescriptionTable 23. DRA
Page 157 and 158: Functional Description5.2.6 Configu
Page 159 and 160: Functional Description5.3.1 GMCH AG
Page 161 and 162: Functional Descriptiondown controll
Page 163 and 164: Functional Description5.3.6 Support
Page 165 and 166: Functional Description5.4.1 3D Engi
Page 167 and 168: Functional DescriptionTexture Forma
Page 169 and 170: Functional DescriptionTexture Map B
Page 171 and 172: Functional DescriptionDepth BufferT
Page 173 and 174: Functional Description5.4.3 Video E
Page 175 and 176: Functional Description5.4.5 PipesSc
Page 177 and 178: Functional DescriptionIntegrated RA
Page 179 and 180: Functional DescriptionDirect YUV fr
Page 181 and 182: Functional Description• System—
Page 183 and 184: Functional Description5.8 ClockingT
Page 185 and 186: Electrical CharacteristicsElectrica
Page 187 and 188: Electrical CharacteristicsTable 36.
Page 189: Electrical Characteristics6.5 DC Pa
Page 193 and 194: Electrical CharacteristicsTable 38.
Page 195 and 196: Electrical Characteristics6.6.3 DAC
Page 197 and 198: Ballout and Package InformationBall
Page 199 and 200: Ballout and Package InformationFigu
Page 201 and 202: Ballout and Package InformationTabl
Page 209 and 210: Ballout and Package Information7.2
Page 211 and 212: TestabilityTestability 8In the GMCH
Page 213 and 214: Testability8.2 XOR Chain Definition
Page 215 and 216: TestabilityTable 45. XOR Chain 1 (3
Page 221 and 222: Intel ® 82865GV GMCHIntel ® 82865
Page 223 and 224: Intel ® 82865GV GMCH9.3 Intel ® 8
Page 225 and 226: Intel ® 82865GV GMCHGMCHCFG—GMCH
Page 227 and 228: Intel ® 82865GV GMCH BalloutIntel
Page 229 and 230: Intel ® 82865GV GMCH BalloutFigure
Page 231 and 232: Intel ® 82865GV GMCH BalloutTable
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Intel ® 82865GV GMCH TestabilityIn
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Intel ® 82865GV GMCH Testability11
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Intel ® 82865GV GMCH TestabilityTa
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IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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