Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.7.6 CC—Class Code Register (Device 2)Address Offset:Default Value:Access:Size:09h−0Bh030000hRO24 bitsThis register contains the device programming interface information related to the Sub-Class Codeand Base Class Code definition for the IGD. This register also contains the Base Class Code andthe function sub-class in relation to the Base Class Code.Bit23:1615:87:0DescriptionBase Class Code (BASEC)—RO.03 = Display controllerSub-Class Code (SCC)—RO.00h = VGA compatible80h = Non-VGA based on device 0 GCBIT 1 as well as Device 0 GC Register Bits 6:4Programming Interface (PI)—RO.00h = Display controller.3.7.7 CLS—Cache Line Size Register (Device 2)Address Offset:Default Value:Access:Size:0Ch00hRO8 bitsThe IGD does not support this register as a PCI slave.Bit7:0DescriptionCache Line Size (CLS)—RO. Hardwired to 00h. The IGD, as a PCI compliant master, does not usethe memory write and Invalidate command and, in general, does not perform operations based oncache line size.3.7.8 MLT2—Master Latency Timer Register (Device 2)Address Offset:Default Value:Access:Size:0Dh00hRO8 bitsThe IGD does not support the programmability of the master latency timer because it does notperform bursts.BitDescription7:0 Master Latency Timer Count Value—RO. Hardwired to 00h.Intel ® 82865G/82865GV GMCH Datasheet 105