Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.6.8 MLT1—Master Latency Timer Register (Device 1)Address Offset:Default Value:Access:Size:0Dh00hRO, R/W8 bitsThis functionality is not applicable. It is described here since these bits should be implemented asread/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.”BitDescriptions7:3Scratchpad MLT (NA7.3)—R/W. These bits return the value with which they are written; however,they have no internal function and are implemented as a scratchpad to avoid confusing software.2:0 Reserved.3.6.9 HDR1—Header Type Register (Device 1)Address Offset:Default Value:Access:Size:0Eh01hRO8 bitsThis register identifies the header layout of the configuration space. No physical register exists atthis location.Bit7:0DescriptionsHeader Type Register (HDR)—RO. This read only field always returns 01 to indicate that GMCHDevice 1 is a single function device with bridge header layout.3.6.10 PBUSN1—Primary Bus Number Register (Device 1)Address Offset:Default Value:Access:Size:18h00hRO8 bitsThis register identifies that virtual PCI-to-PCI bridge is connected to bus 0.Bit7:0DescriptionsPrimary Bus Number (PBUSN)—RO. Configuration software typically programs this field with thenumber of the bus on the primary side of the bridge. Since Device 1 is an internal device and itsprimary bus is always 0, these bits are read only and are hardwired to 0.92 Intel ® 82865G/82865GV GMCH Datasheet