Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Intel ® 82865GV GMCH TestabilityIntel ® 82865GV GMCH Testability 11The chapter provides the testability for the 82865GV component only. In the GMCH, testability forAutomated Test Equipment (ATE) board level testing has been implemented as an XOR chain. AnXOR-tree is a chain of XOR gates, each with one input pin connected to it.11.1 XOR Test Mode InitializationXOR test mode can be entered by driving ADDID6, ADDID7, TESTIN#, PWROK low, andRSTIN# low, then driving PWROK high, then RSTIN# high. XOR test mode via TESTIN# doesnot require a clock. But toggling of HCLKP and HCLKN as shown in Figure 25 is required fordeterministic XOR operation when in AGP 2.0 mode. If the component is in AGP 3.0 mode,ADDID6, ADDID7, and DVOB_BLANK#must be driven high.Figure 25. XOR Toggling of HCLKP and HCLKNPWROK1 msTESTIN#ADDID6MDVI_DATARSTIN#GCLKINHCLKPHCLKNDREFCLKPin testing will not start until RSTIN# is deasserted. Figure 26 shows chains that are testedsequentially. Note that for the GMCH, sequential testing is not required. All chains can be tested inparallel for test time reduction.Intel ® 82865G/82865GV GMCH Datasheet 241