Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.15 GC—Graphics Control Register (Device 0)Address Offset:Default Value:Access:Size:52h0000_1000hR/W, R/W/L8 bitsBitDescriptions7 Reserved6:4Graphics Mode Select (GMS)—R/W/L. This field is used to select the amount of main memory thatis pre-allocated to support the Internal Graphics device in VGA (non-linear) and Native (linear)modes. The BIOS ensures that memory is pre-allocated only when Internal graphics is enabled.000 = No memory pre-allocated. Device 2 (IGD) does not claim VGA cycles (Memory and I/O), andthe Sub-Class Code field within Device 2 function 0 Class Code register is 80. (Default)001 = DVMT (UMA) mode:1 MB of memory pre-allocated for frame buffer.010 = Reserved011 = DVMT (UMA) mode:8 MB of memory pre-allocated for frame buffer.100 = DVMT (UMA) mode:16 MB of memory pre-allocated for frame buffer.101 =Reserved110 = Reserved111 = ReservedNOTE: These register bits are locked and becomes Read Only when the D_LCK bit in the SMRAMregister is set.3Integrated Graphics Disable (IGDIS)—R/W.0 = IGD Enable. When this bit is 0, the GMCH's Device 1 is disabled such that all configurationcycles to Device 1 flow through to HI. Also, the Next_Pointer field in the CAPREG register (Dev0, Offset E4h) will be RO at A0h.1 = IGD is disabled and AGP Graphics is enabled (default). The GMCH's Device 2 and associatedspaces are disabled; all configuration cycles to Device 2 flow through to HI.NOTE: When writing a new value to this bit, software must perform a clock synchronizationsequence.2 ReservedIGD VGA Disable (IVD)—R/W.0 = IGD claims VGA memory and I/O cycles; the Sub-Class Code within Device 2 Class Code1 register is 00h. (Default)1 = IGD does not claim VGA cycles (Memory and I/O); the Sub-Class Code field within Device 2Class Code register is 80h.0 ReservedIntel ® 82865G/82865GV GMCH Datasheet 65