Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.8.15 SSTS3—Secondary Status Register (Device 3)Address Offset:Default Value:Access:Size:1E–1Fh02A0hRO, RWC16 bitsSSTS3 is a 16 bit status register that reports the occurrence of error conditions associated with thesecondary side (i.e., CSA side) of the virtual PCI-to-PCI bridge in the GMCH.Note:For R/WC bits, software must write a 1 to clear bits that are set.BitDescription15 Detected Parity Error (DPE)— RO. Hardwired to 0. Parity is not supported on the CSA interface.1413121110:98Received System Error (RSE)—R/WC.0 = No system error signalled by CSA device.1 = CSA device signals a system error to the GMCH.Received Master Abort Status (RMAS) ⎯R/WC.0 = No master abort by GMCH to terminate a Host-to-CSA transaction.1 = GMCH terminated a Host-to-CSA transaction with an unexpected master abort.Received Target Abort Status (RTAS) ⎯R/WC.0 = No target abort for GMCH-initiated transaction on CSA.1 = GMCH-initiated transaction on CSA is terminated with a target abort.Signaled Target Abort Status (STAS)—RO. Hardwired to 0. The GMCH does not generate atarget abort on CSA.DEVSEL# Timing (DEVT) —RO. Hardwired to 01b. This 2-bit field indicates the timing of theDEVSEL# signal when the GMCH responds as a target on CSA. The 01b value (medium timing)indicates the time when a valid DEVSEL# can be sampled by initiator of the PCI cycle.Master Data Parity Detected (DPD)—RO. Hardwired to 0. GMCH does not implement G_PERR#signal on CSA.Fast Back-to-Back (FB2B)—RO. Hardwired to 1. GMCH, as a target, supports fast back-to-back7transactions on CSA.6 Reserved.5 66/60 MHz PCI Capable (CAP66)—RO. Hardwired to 1. CSA is 66 MHz capable.4:0 Reserved.Intel ® 82865G/82865GV GMCH Datasheet 121