Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.3 Routing Configuration AccessesThe GMCH supports two bus interfaces: HI and AGP/PCI. PCI configuration cycles are selectivelyrouted to one of these interfaces. The GMCH is responsible for routing PCI configuration cycles tothe proper interface. PCI configuration cycles to ICH5 internal devices and Primary PCI (includingdownstream devices) are routed to the ICH5 via HI. AGP/PCI_B configuration cycles are routed toAGP. The AGP/PCI_B interface is treated as a separate PCI bus from a configuration point of view.Routing of configuration AGP/PCI_B is controlled via the standard PCI-to-PCI bridge mechanismusing information contained within the Primary Bus Number, the Secondary Bus Number, and theSubordinate Bus Number registers of the corresponding PCI-to-PCI bridge device.A detailed description of the mechanism for translating processor I/O bus cycles to configurationcycles on one of the buses is described in the following sub-sections.3.3.1 Standard PCI Bus Configuration MechanismThe PCI Bus defines a slot based “configuration space” that allows each device to contain up toeight functions with each function containing up to 256, 8-bit configuration registers. The PCIspecification defines two bus cycles to access the PCI configuration space: Configuration Read andConfiguration Write. Memory and I/O spaces are supported directly by the processor.Configuration space is supported by a mapping mechanism implemented within the GMCH. ThePCI 2.3 specification defines the configuration mechanism to access configuration space. Theconfiguration access mechanism uses the CONFIG_ADDRESS register (at I/O address 0CF8hthough 0CFBh) and CONFIG_DATA register (at I/O address 0CFCh though 0CFFh). To referencea configuration register a DWord I/O write cycle is used to place a value into CONFIG_ADDRESSthat specifies the PCI bus, the device on that bus, the function within the device, and a specificconfiguration register of the device function being accessed. CONFIG_ADDRESS[31] must be 1to enable a configuration cycle. CONFIG_DATA then becomes a window into the four bytes ofconfiguration space specified by the contents of CONFIG_ADDRESS. Any read or write toCONFIG_DATA will result in the GMCH translating the CONFIG_ADDRESS into theappropriate configuration cycle.The GMCH is responsible for translating and routing the processor’s I/O accesses to theCONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH configuration registers,HI, or AGP/PCI_B.3.3.2 PCI Bus #0 Configuration MechanismThe GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of theCONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0, theconfiguration cycle is targeting a PCI Bus 0 device. The Host-HI Bridge entity within the GMCH ishardwired as Device 0 on PCI Bus 0. The Host-AGP/PCI_B Bridge entity within the GMCH ishardwired as Device 1 on PCI Bus 0. Device 6 contains test configuration registers.3.3.3 Primary PCI and Downstream Configuration MechanismIf the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value in the Host-AGP/PCI_B device’s Secondary Bus Number register or greater than the value in the Host-AGP/PCI_B device’s Subordinate Bus Number register, the GMCH generates a Type 1 HI Configuration50 Intel ® 82865G/82865GV GMCH Datasheet