Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Signal Description2.1 Host Interface SignalsSignal Name Type DescriptionADS#BNR#BPRI#BREQ0#BSEL[1:0]CPURST#DBSY#DEFER#DINV[3:0]#I/OAGTL+I/OAGTL+OAGTL+OAGTL+ICMOSOAGTL+I/OAGTL+OAGTL+I/OAGTL+4XAddress Strobe: The processor bus owner asserts ADS# to indicate the first oftwo cycles of a request phase. The GMCH can assert this signal for snoop cyclesand interrupt messages.Block Next Request: BNR# is used to block the current request bus owner fromissuing a new requests. This signal is used to dynamically control the processorbus pipeline depth.Priority Agent Bus Request: The GMCH is the only Priority Agent on theprocessor bus. It asserts this signal to obtain the ownership of the address bus.This signal has priority over symmetric bus requests and will cause the currentsymmetric owner to stop issuing new transactions unless the HLOCK# signal wasasserted.Bus Request 0#: The GMCH pulls the processor bus BREQ0# signal low duringCPURST#. The signal is sampled by the processor on the active-to-inactivetransition of CPURST#. The minimum setup time for this signal is 4 HCLKs. Theminimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. BREQ0#should be terminated high (pulled up) after the hold time requirement has beensatisfied.NOTE: This signal is called BR0# in the Intel ® Pentium ® 4 processorspecifications.Core / FSB Frequency (FSBFREQ) Select Strap: This strap is latched at therising edge of PWROK. These pins has no default internal pull-up resistor.00 = Core frequency is 100 MHz, FSB frequency is 400 MHz01 = Core frequency is 133 MHz, FSB frequency is 533 MHz10 = Core frequency is 200 MHz, FSB frequency is 800 MHz11 = ReservedCPU Reset: The CPURST# pin is an output from the GMCH. The GMCH assertsCPURST# while RSTIN# (PCIRST# from Intel ® ICH5) is asserted and forapproximately 1 ms after RSTIN# is deasserted. The CPURST# allows theprocessors to begin execution in a known state.Note that the ICH5 must provide processor frequency select strap setup and holdtimes around CPURST#. This requires strict synchronization between GMCHCPURST# deassertion and ICH5 driving the straps.Data Bus Busy: This signal is used by the data bus owner to hold the data busfor transfers requiring more than one cycle.Defer: DEFER#, when asserted, indicates that the GMCH will terminate thetransaction currently being snooped with either a deferred response or with aretry response.Dynamic Bus Inversion: DINV[3:0]# are driven along with the HD[63:0]#signals. They Indicate if the associated data signals are inverted. DINV[3:0]# areasserted such that the number of data bits driven electrically low (low voltage)within the corresponding 16-bit group never exceeds 8.DINV[x]# Data BitsDINV3# HD[63:48]#DINV2# HD[47:32]#DINV1# HD[31:16]#DINV0# HD[15:0]#NOTE: This signal is called DBI[3:0] in the processor specifications.Intel ® 82865G/82865GV GMCH Datasheet 27