Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Functional Description5.3.4 AGP Target OperationsAs an initiator, the GMCH does not initiate cycles using AGP enhanced protocols. The GMCHsupports AGP target interface to main memory only. The GMCH supports interleaved AGP andPCI transactions. AGP 2.0 and AGP 3.0 support different command types, as indicated in Table 30.Table 30. AGP 3.0 Commands Compared to AGP 2.0GC/BE[3:0]#(GC#/BE[3:0])EncodingAPG 2.0 CommandAGP 3.0 Command0000 Read (Low Priority) Read (Asynchronous)0001 Read (High Priority) Reserved0010 Reserved Reserved0011 Reserved ISOCH Read (NOT SUPPORTED)0100 Write (Low Priority) Write (Asynchronous)0101 Write (High Priority) Reserved0110 Reserved ISOCH Write, Unfenced (NOT SUPPORTED)0111 Reserved ISOCH Write, Fenced (NOT SUPPORTED)1000 Long Read (Low Priority) Reserved1001 Long Read (High Priority) Reserved1010 Flush (Low Priority) Flush1011 Reserved Reserved)1100 Fence (Low Priority) Fence (for reads and writes)1101 Reserved (was DAC cycle) Reserved (was DAC cycle)1110 Reserved Isoch Align (NOT SUPPORTED)1111 Reserved Reserved5.3.5 AGP Transaction OrderingHigh priority reads and writes are not checked for conflicts between themselves or normal priorityreads and writes. AGP commands (delivered via PIPE# or SBA, not FRAME#) snoop the globalSDRAM write buffer.Table 31. Supported Data RatesData RateSignaling Level0.8 V 1.5 V 3.3 VPCI-66 Yes Yes No1X AGP Yes Yes No2X AGP No See Note No4X AGP Yes Yes No8X AGP Yes No NoNOTE: AGP 2X is not supported on the GMCH.162 Intel ® 82865G/82865GV GMCH Datasheet