Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.20 SMRAM—System Management RAM Control Register(Device 0)Address Offset:Default Value:Access:Size:9Dh02hR/W, RO, Lock8 bitsThe SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces aretreated. The open, close, and lock bits function only when the G_SMRAME bit is set to 1. Also, theopen bit must be reset before the lock bit is set.BitDescriptions7 Reserved.65432:0SMM Space Open (D_OPEN)—R/W. When D_OPEN=1 and D_LCK=0, the SMM space SDRAMis made visible, even when SMM decode is not active. This is intended to help BIOS initialize SMMspace. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time.SMM Space Closed (D_CLS)—R/W. When D_CLS = 1, SMM space SDRAM is not accessible todata references, even if SMM decode is active. Code references may still access SMM spaceSDRAM. This will allow SMM software to reference through SMM space to update the displayeven when SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 andD_CLS=1 are not set at the same time. Note that the D_CLS bit only applies to Compatible SMMspace.SMM Space Locked (D_LCK)—R/W. When D_LCK is set to 1, then D_OPEN is reset to 0 andD_LCK, D_OPEN, C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become read only.D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a FullReset. The combination of D_LCK and D_OPEN provide convenience with security. The BIOS canuse the D_OPEN function to initialize SMM space and then use D_LCK to “lock down” SMM spacein the future so that no application software (or BIOS itself) can violate the integrity of SMM space,even if the program has knowledge of the D_OPEN function.Global SMRAM Enable (G_SMRARE)—R/W/L. If set to 1, Compatible SMRAM functions areenabled, providing 128 KB of SDRAM accessible at the A0000h address while in SMM (ADS# withSMM decode). To enable Extended SMRAM function this bit has to be set to 1. Refer to the sectionon SMM for more details. Once D_LCK is set, this bit becomes read only.Compatible SMM Space Base Segment (C_BASE_SEG)—RO. This field indicates the locationof SMM space. SMM SDRAM is not remapped. It is simply made visible if the conditions are rightto access SMM space, otherwise the access is forwarded to HI. Since the GMCH supports only theSMM space between A0000h and BFFFFh, this field is hardwired to 010.72 Intel ® 82865G/82865GV GMCH Datasheet