Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.6.14 IOBASE1—I/O Base Address Register (Device 1)Address Offset:Default Value:Access:Size:1ChF0hRO, R/W8 bitsThis register controls the processor-to-PCI_B/AGP I/O access routing based on the followingformula:IO_BASE ≤ address ≤ IO_LIMITOnly the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0]are treated as 0. Thus, the bottom of the defined I/O address range will be aligned to a 4-KBboundary.BitDescriptions7:4I/O Address Base (IOBASE)—R/W. This field corresponds to A[15:12] of the I/O addressespassed by bridge 1 to AGP/PCI_B.3:0 Reserved.3.6.15 IOLIMIT1—I/O Limit Address Register (Device 1)Address Offset:Default Value:Access:Size:1Dh00hRO, R/W8 bitsThis register controls the processor-to-PCI_B/AGP I/O access routing based on the followingformula:IO_BASE ≤ address ≤ IO_LIMITOnly the upper 4 bits are programmable. For the purpose of address decode, address bits A[11:0]are assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-KBaligned address block.BitDescriptions7:4I/O Address Limit (IOLIMIT)—R/W. This field corresponds to A[15:12] of the I/O address limit ofDevice 1. Devices between this upper limit and IOBASE1 will be passed to AGP/PCI_B.3:0 Reserved.94 Intel ® 82865G/82865GV GMCH Datasheet