Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.3 PCICMD—PCI Command Register (Device 0)Address Offset: 04–05hDefault Value: 0006hAccess:RO, R/WSize:16 bitsSince GMCH Device 0 does not physically reside on PCI_A, many of the bits are not implemented.Writes to non-implemented bits have no effect.BitDescriptions15:10 Reserved.9Fast Back-to-Back Enable (FB2B)—RO. Hardwired to 0. This bit controls whether or not themaster can do fast back-to-back writes. Since Device 0 is strictly a target, this bit is notimplemented and is hardwired to 0.SERR Enable (SERRE)—R/W. This bit is a global enable bit for Device 0 SERR messaging. TheGMCH does not have a SERR signal. The GMCH communicates the SERR condition by sending aSERR message over HI to the ICH5.0 = Disable. The SERR message is not generated by the GMCH for Device 0. Note that this bit8 only controls SERR messaging for the Device 0. Device 1 has its own SERRE bits to controlerror reporting for error conditions occurring on their respective devices. The control bits areused in a logical OR manner to enable the SERR HI message mechanism.1 = Enable. The GMCH is enabled to generate SERR messages over HI for specific Device 0error conditions that are individually enabled in the ERRCMD register. The error status isreported in the ERRSTS and PCISTS registers.7 Address/Data Stepping Enable (ADSTEP)—RO. Hardwired to 0.Parity Error Enable (PERRE)—RO. Hardwired to 0. The PERR# signal is not implemented by the6GMCH.5 VGA Palette Snoop Enable (VGASNOOP)—RO. Hardwired to 0.Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0. The GMCH will never issue4memory write and invalidate commands.3 Special Cycle Enable (SCE)—RO. Not implemented; hardwired to 0.2 Bus Master Enable (BME)—RO. Hardwired to 1. GMCH is always enabled as a master on HI.Memory Access Enable (MAE)—RO. Hardwired to 1. The GMCH always allows access to main1memory.0 I/O Access Enable (IOAE)—RO. Hardwired to 0.58 Intel ® 82865G/82865GV GMCH Datasheet