Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.7.19 MINGNT—Minimum Grant Register (Device 2)Address Offset:Default Value:Access:Size:3Eh00hRO8 bitsBitDescription7:0 Minimum Grant Value—RO. Hardwired to 00h. The IGD does not burst as a PCI compliant master.3.7.20 MAXLAT—Maximum Latency Register (Device 2)Address Offset:Default Value:Access:Size:3Fh00hRO8 bitsBit7:0DescriptionMaximum Latency Value—RO. Hardwired to 00h. The IGD has no specific requirements for howoften it needs to access the PCI bus.3.7.21 PMCAPID—Power Management Capabilities IdentificationRegister (Device 2)Address Offset:Default Value:Access:Size:D0h−D1h0001hRO16 bitsBitDescription15:8NEXT_PTR—RO. This field contains a pointer to next item in the capabilities list. This is the finalcapability in the list and must be set to 00h.7:0 CAP_ID—RO. SIG defines this ID as 01h for power management.110 Intel ® 82865G/82865GV GMCH Datasheet