Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

System Address Map4.4 AGP Memory Address RangesThe GMCH can be programmed to direct memory accesses to the AGP bus interface whenaddresses are within either of two ranges specified via registers in GMCH’s Device 1 configurationspace. The first range is controlled via the Memory Base (MBASE) and Memory Limit (MLIMIT)registers. The second range is controlled via the Prefetchable Memory Base (PMBASE) andPrefetchable Memory Limit (PMLIMIT) registers.Conceptually, address decoding for each range follows the same basic concept. The top 12 bits ofthe respective Memory Base and Memory Limit registers correspond to address bits A[31:20] of amemory address. For the purpose of address decoding, the GMCH assumes that address bitsA[19:0] of the memory base are zero and that address bits A[19:0] of the memory limit address areFFFFFh. This forces each memory address range to be aligned to 1-MB boundary and to have asize granularity of 1 MB.The GMCH positively decodes memory accesses to AGP memory address space as defined by thefollowing equations:Memory_Base_Address ≤ Address ≤ Memory_Limit_AddressPrefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_AddressThe window size is programmed by the plug-and-play configuration software. The window sizedepends on the size of memory claimed by the AGP device. Normally, these ranges reside abovethe top of main memory and below High BIOS and APIC address ranges. They normally resideabove the top of memory (TOUD) so they do not steal any physical SDRAM memory space.It is essential to support a separate Prefetchable range in order to apply the USWC attribute (fromthe processor point of view) to that range. The USWC attribute is used by the processor for writecombining.Note that the GMCH Device 1 memory range registers described above are used to allocatememory address space for any devices on AGP that require such a window. These devices includethe AGP device, PCI-66 MHz/1.5 V agents, and multifunctional AGP devices where one or morefunctions are implemented as PCI devices.The PCICMD1 register can override the routing of memory accesses to AGP. In other words, thememory access enable bit must be set in the device 1 PCICMD1 register to enable the memorybase/limit and prefetchable base/limit windows.146 Intel ® 82865G/82865GV GMCH Datasheet