Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.6.3 PCICMD1—PCI Command Register (Device 1)Address Offset: 04–05hDefault Value: 0000hAccess:RO, R/WSize:16 bitsBitDescriptions15:10 Reserved.9 Fast Back-to-Back Enable (FB2B)—RO. Hardwired to 0.SERR Message Enable (SERRE)—R/W. This bit is a global enable bit for Device 1 SERRmessaging. The GMCH communicates the SERR# condition by sending a SERR message to theICH5.8 0 = Disable. SERR message is not generated by the GMCH for Device 1.1 = Enable. GMCH is enabled to generate SERR messages over HI for specific Device 1 errorconditions that are individually enabled in the BCTRL1 register. The error status is reported inthe PCISTS1 register.7 Address/Data Stepping (ADSTEP)—RO. Hardwired to 0.Parity Error Enable (PERRE)—RO. Hardwired to 0. Parity checking is not supported on the6primary side of this device.5 Reserved.4 Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0.3 Special Cycle Enable (SCE)—RO. Hardwired to 0.210Bus Master Enable (BME)—R/W.0 = Disable. AGP Master initiated Frame# cycles will be ignored by the GMCH. The result is amaster abort. Ignoring incoming cycles on the secondary side of the PCI-to-PCI bridgeeffectively disabled the bus master on the primary side. (default)1 = Enable. AGP master initiated Frame# cycles will be accepted by the GMCH if they hit a validaddress decode range. This bit has no affect on AGP Master originated SBA or PIPE# cycles.Memory Access Enable (MAE)—R/W.0 = Disable. All of Device 1’s memory space is disabled.1 = Enable. Enables the memory and pre-fetchable memory address ranges defined in theMBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.IO Access Enable (IOAE)—R/W.0 = Disable. All of Device 1’s I/O space is disabled.1 = Enable. This bit must be set to1 to enable the I/O address range defined in the IOBASE1, andIOLIMIT1 registers.Intel ® 82865G/82865GV GMCH Datasheet 89