Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.8.17 MLIMIT3—Memory Limit Address Register (Device 3)Address Offset: 22–23hDefault Value: 0000hAccess:RO, R/WSize:16 bitsThis register controls the processor-to-CSA non-prefetchable memory access routing based on thefollowing formula:MEMORY_BASE ≤ address ≤ MEMORY_LIMITThe upper 12 bits of the register are read/write and correspond to the upper 12 address bitsA[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeroeswhen read. This register must be initialized by the configuration software. For the purpose ofaddress decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the definedmemory address range will be at the top of a 1-MB aligned memory block.Note:Note:Memory ranges covered by the MBASE and MLIMIT registers are used to map non-prefetchableCSA address ranges (typically, where control/status memory-mapped I/O data structures of thegraphics controller will reside) and the PMBASE and PMLIMIT registers are used to mapprefetchable address ranges (typically, graphics local memory). This segregation allows applicationof USWC space attribute to be performed in a true plug-and-play manner to the prefetchableaddress range for improved Processor-CSA memory access performance.Configuration software is responsible for programming all address range registers (prefetchable,non-prefetchable) with the values that provide exclusive address ranges (i.e., prevent overlap witheach other and/or with the ranges covered with the main memory). There is no provision in theGMCH hardware to enforce prevention of overlap and operations of the system in the case ofoverlap are not guaranteed.Bit15:4DescriptionMemory Address Limit (MLIMIT)—R/W. This field corresponds to A[31:20] of the memory addressthat corresponds to the upper limit of the range of memory accesses that will be passed by theDevice 3 bridge to CSA.3:0 Reserved.Intel ® 82865G/82865GV GMCH Datasheet 123