IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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Intel ® 82865GV GMCH TestabilityFigure 26. XOR Testing Chains Tested SequentiallyPWROK5 ms 10 ms 15 ms 20 msTESTIN#RSTIN#ADDID6MDVI_DATAGCLKINHCLKPHCLKNDREFCLKSDM_A0SDM_A1SDM_A2SDM_A3SDM_A4SDM_A5SDM_A6SDM_A7HTRDY#RS2#RS0#BREQ0#242 Intel ® 82865G/82865GV GMCH Datasheet
Intel ® 82865GV GMCH Testability11.2 XOR Chain DefinitionThe GMCH has 10 XOR chains. The XOR chain outputs are driven out on the output pins asshown in Table 56. During fullwidth testing, XOR chain outputs will be visible on both pins(For example, xor_out0 will be visible on SDM_A0 and SDM_B0). During channel shared modeon the tester, outputs will be visible on their respective channels. (For example, in channel A mode,xor_out0 will be visible on SDM_A0 and the same will be visible on SDM_B0 in channel Bmode.)Table 56. XOR Chain OutputsXOR Chain DDR Output Pin Channel A DDR Output Pin Channel Bxor_out0 SDM_A0 SDM_B0xor_out1 SDM_A1 SDM_B1xor_out2 SDM_A2 SDM_B2xor_out3 SDM_A3 SDM_B3xor_out4 SDM_A4 SDM_B4xor_out5 SDM_A5 SDM_B5xor_out6 SDM_A6 SDM_B6xor_out7 SDM_A7 SDM_B7xor_out8 HTRDY# BPRI#xor_out9 RS2# DEFER#xor_out10 RS0# RS1#xor_out11 BREQ0# CPURST#The following tables show the XOR chain pin mappings and their monitors for the GMCH.Note: Notes for Table 57 through Table 67.1. All XOR chains can be run in parallel, except chains 0 and 1, chains 0 and 2, and chains 2 and4).2. The channel A and channel B output pins for each chain show the same output.Intel ® 82865G/82865GV GMCH Datasheet 243
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Intel ® 865G/865GV ChipsetDatashee
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Contents1 Introduction.............
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3.8 PCI-to-CSA Bridge Registers (De
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5.5.3 Synchronous Display .........
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Tables1 General Terminology .......
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Introduction1.4 Intel ® 82865G GMC
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Introduction1.4.7 Display Interface
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Signal Description2.1 Host Interfac
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Signal DescriptionSignal Name Type
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Signal Description2.2.2 DDR SDRAM C
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Signal Description2.5 AGP Interface
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Signal Description2.5.4 AGP Strobes
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Signal DescriptionSignal Name Type
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Signal Description2.5.7 Intel ® DV
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Signal Description2.7 Clocks, Reset
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Signal Description2.10 GMCH Sequenc
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Signal Description2.12 Full and War
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Register DescriptionTermReservedReg
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Register Description3.3 Routing Con
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Register DescriptionIf the Bus Numb
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Register Description3.4.2 CONFIG_DA
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Register DescriptionTable 6.DRAM Co
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Register Description3.5.3 PCICMD—
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Register Description3.5.5 RID—Rev
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Register Description3.5.10 APBASE
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Register Description3.5.14 AGPM—A
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Register DescriptionNotes on Pre-Al
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Register Description3.5.17 FPLLCONT
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Register DescriptionAs an example,
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Register Description3.5.20 SMRAM—
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Register Description3.5.22 ACAPID
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Register Description3.5.24 AGPCMD
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Register Description3.5.26 APSIZE
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Register Description3.5.29 LPTT—A
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Register Description3.5.31 GMCHCFG
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Register Description3.5.32 ERRSTS
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Register Description3.5.34 SKPD—S
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Register Description3.6.1 VID1—Ve
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Register Description3.6.4 PCISTS1
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Register Description3.6.8 MLT1—Ma
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Register Description3.6.14 IOBASE1
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Register Description3.6.17 MBASE1
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Register Description3.6.22 ERRCMD1
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Register Description3.7.6 CC—Clas
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Register Description3.7.11 MMADR—
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Register Description3.7.16 CAPPOINT
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Register Description3.7.22 PMCAP—
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Register Description3.8 PCI-to-CSA
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Register Description3.8.3 PCICMD3
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Register Description3.8.5 RID3—Re
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Register Description3.8.11 SBUSN3
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Register Description3.8.15 SSTS3—
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Register Description3.8.17 MLIMIT3
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Register Description3.8.20 BCTRL3
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Register Description3.9 Overflow Co
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Register Description3.9.4 PCISTS6
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Register Description3.9.9 BAR6—Me
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Register DescriptionThe remaining 7
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Register Description3.10.3 DRT—DR
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Register DescriptionBit6:4Descripti
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System Address MapSystem Address Ma
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System Address Map4.2 Compatibility
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System Address Map4.3 Extended Memo
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System Address MapPCI Memory Addres
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Functional DescriptionFunctional De
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Functional Description5.2 System Me
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Functional Description5.2.2.1 Dynam
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Functional DescriptionTable 21. DRA
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Functional DescriptionTable 23. DRA
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Functional Description5.2.6 Configu
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Functional Description5.3.1 GMCH AG
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Functional Descriptiondown controll
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Functional Description5.3.6 Support
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Functional Description5.4.1 3D Engi
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Functional DescriptionTexture Forma
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Functional DescriptionTexture Map B
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Functional DescriptionDepth BufferT
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Functional Description5.4.3 Video E
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Functional Description5.4.5 PipesSc
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Functional DescriptionIntegrated RA
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Functional DescriptionDirect YUV fr
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Functional Description• System—
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Functional Description5.8 ClockingT
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Electrical CharacteristicsElectrica
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Electrical CharacteristicsTable 36.
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Electrical Characteristics6.5 DC Pa
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Page 193 and 194: Electrical CharacteristicsTable 38.
Page 195 and 196: Electrical Characteristics6.6.3 DAC
Page 197 and 198: Ballout and Package InformationBall
Page 199 and 200: Ballout and Package InformationFigu
Page 201 and 202: Ballout and Package InformationTabl
Page 209 and 210: Ballout and Package Information7.2
Page 211 and 212: TestabilityTestability 8In the GMCH
Page 213 and 214: Testability8.2 XOR Chain Definition
Page 215 and 216: TestabilityTable 45. XOR Chain 1 (3
Page 221 and 222: Intel ® 82865GV GMCHIntel ® 82865
Page 223 and 224: Intel ® 82865GV GMCH9.3 Intel ® 8
Page 225 and 226: Intel ® 82865GV GMCHGMCHCFG—GMCH
Page 227 and 228: Intel ® 82865GV GMCH BalloutIntel
Page 229 and 230: Intel ® 82865GV GMCH BalloutFigure
Page 231 and 232: Intel ® 82865GV GMCH BalloutTable
Page 241: Intel ® 82865GV GMCH TestabilityIn
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IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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