IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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TestabilityTable 47. XOR Chain 3 (41 Inputs) Output Pins: SDM_A3, SDM_B3Signal Name Ball Number Signal Name Ball Number Signal Name Ball NumberBNR# B28 HA12# B31 HA19# F28BSEL1 L12 HA9# C30 HA18# C32HIT# K21 HA22# G27DRDY# G24 HA4# D30 HA24# E28DBSY# E27 HA10# C31 HA23# F29ADS# F27 HA15# J24 HADSTB1# D28HREQ4# J21 HA8# K23 HA17# D34HA16# F25 HA13# E30 HA25# H27HREQ3# C29 HA6# E29 HA20# C34HREQ0# B29 HA5# L23 HA30# J26HA3# D26 HA11# J25 HA21# J27HREQ1# J23 HREQ2# L22 HA27# E32HA7# B32 HA31# G26 HA29# G30HA14# B33 HA26# K24 HA28# F31Output PinsSDM_A3SDM_B3AP30AJ28Table 48. XOR Chain 4 (40 Inputs) Output Pins: SDM_A4, SDM_B4Signal Name Ball Number Signal Name Ball Number Signal Name Ball NumberHD45# H10 HD43# K13 HD57# C11HD46# G8 HD33# L16 HDSTBP3# D12HD40# G10 HD41# L15 HDSTBN3# E12HD47# E9 HD35# F13 HD51# B12HD39# G12 HD32# J15 HD49# E14HD36# F11 HD37# E13 HD55# B11HD44# J11 HD58# E10 HD54# C13HD42# E11 HD56# D10 HD53# D14DINV2# L14 HD62# D8 HD50# B14HDSTBP2# G9 HD61# B9 HD48# B13HDSTBN2# F9 HD63# B8 HD52# B15HD34# J13 HD59# B10 DINV3# C15HD38# K15 HD60# C9 GADSTBF1 V4Output Pins HSYNC G3SDM_A1SDM_B1AF31AC31216 Intel ® 82865G/82865GV GMCH Datasheet
TestabilityTable 49. XOR Chain 5 (44 Inputs) Output Pins: SDM_A5, SDM_B5Signal Name Ball Number Signal Name Ball Number Signal Name Ball NumberSDQ_A58 E33 SDQ_A53 P34 SDQ_A41 AB31SDQ_A59 F33 SDQ_A48 T34 SDQ_A44 AD31SDQ_A62 G34 SDQ_A52 T31 SDQS_A4 AF34SDQ_A63 F34 SDQ_A49 T32 SDQ_A35 AD32SDQS_A7 H31 SCMDCLK_A5# P32 SDQ_A38 AE34SDQ_A61 J34 SCMDCLK_A5 P31 SDQ_A39 AD34SDQ_A57 H34 SCMDCLK_A2# N34 SDQ_A34 AF32SDQ_A56 J33 SCMDCLK_A2 N33 SDQ_A33 AG34SDQ_A60 K31 SDQS_A5 V34 SDQ_A37 AG33SDQ_A51 K32 SDQ_A42 V32 SDQ_A36 AH31SDQ_A50 K34 SDQ_A46 U34 SDQ_A32 AH32SDQ_A55 L33 SDQ_A47 U33 SCMDCLK_A0 AK32SDQS_A6 M32 SDQ_A43 V31 SCMDCLK_A0# AK31SDQ_A54 L34 SDQ_A40 AC34 SCMDCLK_A3# AK34SDQ_A45 AB32 SCMDCLK_A3 AK33Output PinsSDM_A1SDM_B1W33U31Table 50. XOR Chain 6 (40 Inputs) Output Pins: SDM_A6, SDM_B6Signal Name Ball Number Signal Name Ball Number Signal Name Ball NumberSDQ_A30 AM31 SDQ_A19 AN27 SDQ_A8 AP14SDQS_A3 AM30 SDQ_A23 AP27 SDQ_A6 AL12SDQ_A27 AM33 SDQ_A22 AP25 SDQ_A2 AM12SDQ_A31 AN34 SDQ_A16 AP22 SDQ_A3 AN13SDQ_A29 AN29 SDQ_A20 AP21 SDQS_A0 AN11SDQ_A26 AP33 SDQ_A10 AL18 SDQ_A5 AL10SDQ_A25 AP29 SDQ_A15 AM18 SDQ_A7 AP13SDQ_A24 AP28 SDQ_A14 AP18 SDQ_A4 AM10SDQ_A28 AM28 SDQS_A1 AP15 SCMDCLK_A1 AP17SDQS_A2 AP23 SDQ_A11 AP19 SCMDCLK_A1# AN17SDQ_A21 AL22 SDQ_A13 AN15 SDQ_A1 AP11SDQ_A17 AM22 SDQ_A9 AM14 SCMDCLK_A4# AL16SDQ_A18 AL24 SDQ_A12 AL14 SCMDCLK_A4 AM16SDQ_A0AP10Output PinsSDM_A6SDM_B6M34M29Intel ® 82865G/82865GV GMCH Datasheet 217
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Intel ® 865G/865GV ChipsetDatashee
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Contents1 Introduction.............
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3.8 PCI-to-CSA Bridge Registers (De
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5.5.3 Synchronous Display .........
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Tables1 General Terminology .......
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Introduction1.4 Intel ® 82865G GMC
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Introduction1.4.7 Display Interface
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Signal Description2.1 Host Interfac
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Signal DescriptionSignal Name Type
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Signal Description2.2.2 DDR SDRAM C
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Signal Description2.5 AGP Interface
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Signal Description2.5.4 AGP Strobes
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Signal DescriptionSignal Name Type
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Signal Description2.5.7 Intel ® DV
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Signal Description2.7 Clocks, Reset
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Signal Description2.10 GMCH Sequenc
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Signal Description2.12 Full and War
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Register DescriptionTermReservedReg
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Register Description3.3 Routing Con
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Register DescriptionIf the Bus Numb
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Register Description3.4.2 CONFIG_DA
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Register DescriptionTable 6.DRAM Co
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Register Description3.5.3 PCICMD—
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Register Description3.5.5 RID—Rev
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Register Description3.5.10 APBASE
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Register Description3.5.14 AGPM—A
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Register DescriptionNotes on Pre-Al
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Register Description3.5.17 FPLLCONT
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Register DescriptionAs an example,
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Register Description3.5.20 SMRAM—
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Register Description3.5.22 ACAPID
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Register Description3.5.24 AGPCMD
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Register Description3.5.26 APSIZE
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Register Description3.5.29 LPTT—A
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Register Description3.5.31 GMCHCFG
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Register Description3.5.32 ERRSTS
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Register Description3.5.34 SKPD—S
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Register Description3.6.1 VID1—Ve
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Register Description3.6.4 PCISTS1
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Register Description3.6.8 MLT1—Ma
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Register Description3.6.14 IOBASE1
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Register Description3.6.17 MBASE1
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Register Description3.6.22 ERRCMD1
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Register Description3.7.6 CC—Clas
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Register Description3.7.11 MMADR—
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Register Description3.7.16 CAPPOINT
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Register Description3.7.22 PMCAP—
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Register Description3.8 PCI-to-CSA
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Register Description3.8.3 PCICMD3
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Register Description3.8.5 RID3—Re
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Register Description3.8.11 SBUSN3
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Register Description3.8.15 SSTS3—
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Register Description3.8.17 MLIMIT3
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Register Description3.8.20 BCTRL3
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Register Description3.9 Overflow Co
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Register Description3.9.4 PCISTS6
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Register Description3.9.9 BAR6—Me
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Register DescriptionThe remaining 7
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Register Description3.10.3 DRT—DR
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Register DescriptionBit6:4Descripti
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System Address MapSystem Address Ma
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System Address Map4.2 Compatibility
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System Address Map4.3 Extended Memo
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System Address MapPCI Memory Addres
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Functional DescriptionFunctional De
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Functional Description5.2 System Me
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Functional Description5.2.2.1 Dynam
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Functional DescriptionTable 21. DRA
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Functional DescriptionTable 23. DRA
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Functional Description5.2.6 Configu
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Functional Description5.3.1 GMCH AG
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Functional Descriptiondown controll
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Functional Description5.3.6 Support
Page 165 and 166: Functional Description5.4.1 3D Engi
Page 167 and 168: Functional DescriptionTexture Forma
Page 169 and 170: Functional DescriptionTexture Map B
Page 171 and 172: Functional DescriptionDepth BufferT
Page 173 and 174: Functional Description5.4.3 Video E
Page 175 and 176: Functional Description5.4.5 PipesSc
Page 177 and 178: Functional DescriptionIntegrated RA
Page 179 and 180: Functional DescriptionDirect YUV fr
Page 181 and 182: Functional Description• System—
Page 183 and 184: Functional Description5.8 ClockingT
Page 185 and 186: Electrical CharacteristicsElectrica
Page 187 and 188: Electrical CharacteristicsTable 36.
Page 189 and 190: Electrical Characteristics6.5 DC Pa
Page 195 and 196: Electrical Characteristics6.6.3 DAC
Page 197 and 198: Ballout and Package InformationBall
Page 199 and 200: Ballout and Package InformationFigu
Page 201 and 202: Ballout and Package InformationTabl
Page 209 and 210: Ballout and Package Information7.2
Page 211 and 212: TestabilityTestability 8In the GMCH
Page 213 and 214: Testability8.2 XOR Chain Definition
Page 215: TestabilityTable 45. XOR Chain 1 (3
Page 219 and 220: TestabilityTable 53. XOR Chain 9 (6
Page 221 and 222: Intel ® 82865GV GMCHIntel ® 82865
Page 223 and 224: Intel ® 82865GV GMCH9.3 Intel ® 8
Page 225 and 226: Intel ® 82865GV GMCHGMCHCFG—GMCH
Page 227 and 228: Intel ® 82865GV GMCH BalloutIntel
Page 229 and 230: Intel ® 82865GV GMCH BalloutFigure
Page 231 and 232: Intel ® 82865GV GMCH BalloutTable
Page 241 and 242: Intel ® 82865GV GMCH TestabilityIn
Page 243 and 244: Intel ® 82865GV GMCH Testability11
Page 245 and 246: Intel ® 82865GV GMCH TestabilityTa
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IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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