Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.31 GMCHCFG—GMCH Configuration Register (Device 0)Address Offset:Default Value:Access:Size:C6–C7h0000hR/W, RO16 bitsBitDescriptionsNumber of Stop Grant Cycles (NSG)—R/W. This field contains the number of Stop Granttransactions expected on the FSB bus before a Stop Grant Acknowledge packet is sent to theICH5. This field is programmed by the BIOS after it has enumerated the processors and before ithas enabled Stop Clock generation in the ICH5. Once this field has been set, it should not bemodified. Note that each enabled thread within each processor will generate Stop Grant15:13Acknowledge transactions.000 = HI Stop Grant sent after 1 FSB Stop Grant001 = HI Stop Grant sent after 2 FSB Stop Grants010–111= Reserved12 ReservedSystem Memory Frequency Select (SMFREQ)—R/W. Default = 00. The DDR memoryfrequency is determined by the following table and partly determined by the FSB frequency.FSBFREQ[1:0] =00 SMFREQ[11:10]=01 System Memory DDR set to 266 MHzFSBFREQ[1:0] =01 SMFREQ[11:10]=00 System Memory DDR set to 266 MHzFSBFREQ[1:0] =01 SMFREQ[11:10]=01 System Memory DDR set to 333 MHz11:10 FSBFREQ[1:0] =10 SMFREQ[11:10]=01 System Memory DDR set to 333 (320) MHzFSBFREQ[1:0] =10 SMFREQ[11:10]=10 System Memory DDR set to 400 MHzAll others are ReservedNote that Memory I/O Clock always runs at 2x the frequency of the memory clock.When writing a new value to this register, software must perform a clock synchronizationsequence to apply the new timings. The new value does not get applied until this is completed.9:6 ReservedMDA Present (MDAP)—R/W. This bit works with the VGA Enable bits in the BCTRL1 register ofDevice 1 to control the routing of processor-initiated transactions targeting MDA compatible I/Oand memory address ranges. This bit should not be set if Device 1's VGA Enable bit is not set. IfDevice 1's VGA enable bit is not set, then accesses to I/O address range x3BCh–x3BFh areforwarded to HI. If the VGA enable bit is not set, then accesses to I/O address range x3BCh–x3BFh are treated just like any other I/O accesses. That is, the cycles are forwarded to AGP if theaddress is within the corresponding IOBASE and IOLIMIT and ISA enable bit is not set; otherwise,they are forwarded to HI. MDA resources are defined as the following:Memory: 0B0000h – 0B7FFFhI/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,5(including ISA address aliases, A[15:10] are not used in decode)Any I/O reference that includes the I/O locations listed above, or their aliases, will be forwarded tothe hub interface, even if the reference includes I/O locations not listed above.The following table shows the behavior for all combinations of MDA and VGA:VGA MDA Behavior0 0 All references to MDA and VGA go to HI.0 1 Illegal combination (DO NOT USE).1 0 All references to VGA go to Device 1.MDA-only references (I/O address 3BFh and aliases) will go to HI.1 1 VGA references go to AGP/PCI; MDA references go to HI.4 Reserved82 Intel ® 82865G/82865GV GMCH Datasheet