Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.9.4 PCISTS6—PCI Status Register (Device 6)Address Offset: 06–07hDefault Value: 0080hAccess:ROSize:16 bitsPCISTS6 is a 16-bit status register that reports the occurrence of error events on Device 6, Function0’s PCI interface. Since GMCH Device 6 does not physically reside on PCI_0, many of the bits arenot implemented.BitDescriptions15 Detected Parity Error (DPE)—RO. Hardwired to 0.14 Signaled System Error (SSE)—RO. Hardwired to 0.13 Received Master Abort Status (RMAS)—RO. Hardwired to 0.12 Received Target Abort Status (RTAS)—RO. Hardwired to 0.11 Signaled Target Abort Status (STAS)—RO. Hardwired to 0.DEVSEL Timing (DEVT)—RO. Hardwired to 00b. Device 6 does not physically connect to PCI_A.10:9 These bits are set to 00b (fast decode) so that optimum DEVSEL timing for PCI_A is not limited bythe GMCH.8 Master Data Parity Error Detected (DPD)—RO. Hardwired to 0.Fast Back-to-Back (FB2B)—RO. Hardwired to 1. This indicates fast back-to-back capability;7thus, the optimum setting for PCI_A is not limited by the GMCH.6:0 Reserved.3.9.5 RID6—Revision Identification Register (Device 6)Address Offset:Default Value:Access:Size:08hSee table belowRO8 bitsThis register contains the revision number of the GMCH Device 0.Bit7:0DescriptionsRevision Identification Number (RID)—RO. This is an 8-bit value that indicates the revisionidentification number for the GMCH Device 6. This value is the same as the RID register.02h = A-2 SteppingIntel ® 82865G/82865GV GMCH Datasheet 129