Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.8.4 PCISTS3—PCI Status Register (Device 3)Address Offset:Default Value:Access:Size:06h−07h00A0hRO, R/WC16 bitsPCISTS3 is a 16-bit status register that reports the occurrence of error conditions associated withprimary side of the virtual PCI-to-CSA bridge in the GMCH.Note:For R/WC bits, software must write a 1 to clear bits that are set.BitDescription151413121110:98Detected Parity Error (DPE)⎯RO. Hardwired to 0. Parity is not supported on the primary side ofthis device.Signaled System Error (SSE)⎯R/WC.0 = No SERR message generated by GMCH Device 3 over HI.1 = GMCH Device 3 generated a SERR message over HI for any enabled Device 3 error condition.Device 3 error conditions are enabled in the ERRCMD, PCICMD3, and BCTRL3 registers.Device 3 error flags are read/reset from the ERRSTS and SSTS3 register.Received Master Abort Status (RMAS)⎯RO. Hardwired to 0. The concept of a master abort doesnot exist on the primary side of this device.Received Target Abort Status (RTAS)⎯RO. Hardwired to 0. The concept of a target abort doesnot exist on the primary side of this device.Signaled Target Abort Status (STAS)—RO. Hardwired to 0. The concept of a target abort does notexist on primary side of this device.DEVSEL# Timing (DEVT)—RO. The Hardwired to 00b. GMCH does not support subtractivedecoding devices on bus 0. The value 00b indicates that Device 3 uses the fastest possible decode.Data Parity Detected (DPD)⎯RO. Hardwired to 0. Parity Error Response is hardwired to disabled(and the GMCH does not support any parity detection on the primary side of this device).Fast Back-to-Back (FB2B)—RO. Hardwired to 1. The interface always supports fast back-to-back7writes.6 Reserved.5 66/60 MHz PCI Capable (CAP66)—RO. Hardwired to 1. CSA is 66 MHz capable.4:0 Reserved.116 Intel ® 82865G/82865GV GMCH Datasheet