Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register DescriptionThe remaining 7 bits of each of these registers are compared against address lines 31:26 todetermine which row is being addressed by the current cycle. In either of the dual-channel modes,the GMCH supports a total of 4 rows of memory (only DRB0:3 are used). When in either of thedual-channel modes and four rows populated with 512-Mb technology, x8 devices, the largestmemory size of 4 GB is supported. In this case, DRB3 is programmed to 40h. In the dual-channelmodes, DRB[7:4] must be programmed to the same value as DRB3. In single-channel mode, alleight DRB registers are used. In this case, DRB[3:0] are used for the rows in channel A andDRB[7:4] are used for rows populated in channel B. If only channel A is populated, then onlyDRB[3:0] are used. DRB[7:4] are programmed to the same value as DBR3. If only channel B ispopulated, then DRB[7:4] are used and DRB[3:0] are programmed to 00h. When both channels arepopulated but not identically, all of the DRB registers are used. This configuration is referred to as“virtual single-channel mode.”Row0: 0000hRow1: 0001hRow2: 0002hRow3: 0003hRow4: 0004hRow5: 0005hRow6: 0006hRow7: 0007h0008h, reserved0009h, reserved000Ah, reserved000Bh, reserved000Ch, reserved000Dh, reserved000Eh, reserved000Fh, reservedDRB0 = Total memory in Row0 (in 64-MB increments)DRB1 = Total memory in Row0 + Row1 (in 64-MB increments)DRB2 = Total memory in Row0 + Row1 + Row2 (in 64-MB increments)DRB3 = Total memory in Row0 + Row1 + Row2 + Row3 (in 64-MB increments)DRB4 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 (in 64-MB increments)DRB5 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 + Row5 (in 64-MB increments)DRB6 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 + Row5 + Row6(in 64-MB increments)DRB7 = Total memory in Row0 + Row1 + Row2 + Row3 + Row4 + Row5 + Row6 + Row7(in 64-MB increments)Each row is represented by a byte. Each byte has the following format:BitDescription7 Reserved.6:0DRAM Row Boundary Address—R/W. This 7-bit value defines the upper and lower addresses foreach SDRAM row. This 7-bit value is compared against address lines 0,31:26 (0 concatenated withthe address bits 31:26) to determine which row the incoming address is directed.Default= 0000001bIntel ® 82865G/82865GV GMCH Datasheet 133