Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.17 FPLLCONT— Front Side Bus PLL Clock Control Register(Device 0)Address Offset:Default Value:Access:Size:60h00hR/W, RO8 bitsThese register bits are used for changing DDR frequency initializing GMCH memory and I/Oclocks WIO DLL delays, and initializing internal graphics controller's clocks and resets.BitDescriptions7:5 Reserved.4Memory and Memory I/O DLL Clock Gate (DLLCKGATE)—R/W.0 = Writing a 0 will cleanly re-enable the memory and memory I/O clocks from the DLL outputs.1 = Writing a 1 will cleanly disable the memory and memory IO clocks of the chipset core andDDR interface from the DLL outputs.NOTE: This bit should always be written to before writing to the FPLLSYNC bit.3210Graphics Activate (GFXACT)—R/W.1 = After propagating the internal graphics enable, writing a 1 to this bit will cause the internalgraphics logic to come out of reset. After a 1 has been written, the GMCH will take the internalgraphics logic out of reset. From then on, the internal graphics can only be put back into resetwith a hardware reset.Propagate Internal Graphics Enable (PIGE)—R/W.0 = This bit should be set to 0 shortly after setting it to 1, though no action is taken on writing a 0.1 = After writing a 0 to IGDIS (Dev 0, Offset 52, bit 3) to enable internal graphics, writing a 1 tothis bit will propagate the IGDIS register to the chip which will make the configuration spacefor Device 1 (AGP Bridge) disappear and Device 2 (integrated graphics) appear. Propagatingthe IGE will also enable the graphics clock.FSB PLL Sync (FPLLSYNC)—R/W.0 = After writing a 1, writing a 0 will cause the FSB PLL to synchronize the memory and graphicscore clocks to the processor clock.1 = Writing a 1 will reset the memory and core graphics clock dividers in the FSB FPLL. This willalso enable the output of the system memory frequency bits and the Graphics Clock TestMode register to propagate to the chip and the FPLL.Graphics/Memory Clock Gate (GMCLKGATE)—R/W.0 = Writing a 0 restarts (enable) the clocks.1 = Writing a 1 cleanly disables the graphics and memory clocks while still enabling the coreclocks. The memory and graphics clocks can then be programmed with new speedinformation.NOTE: This bit should always be written to before writing to the FPLLSYNC bit.68 Intel ® 82865G/82865GV GMCH Datasheet