IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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Register Description3.4.2 CONFIG_DATA—Configuration Data RegisterI/O Address:Default Value:Access:Size:0CFCh–0CFFh00000000hR/W32 bitsCONFIG_DATA is a 32-bit read/write window into configuration space. The portion ofconfiguration space that is referenced by CONFIG_DATA is determined by the contents ofCONFIG_ADDRESS.Bit31:0DescriptionsConfiguration Data Window (CDW). If bit 31 of CONFIG_ADDRESS is 1, any I/O access toCONFIG_DATA are mapped to configuration space using the contents of CONFIG_ADDRESS.54 Intel ® 82865G/82865GV GMCH Datasheet
Register Description3.5 DRAM Controller/Host-Hub Interface DeviceRegisters (Device 0)This section contains the DRAM Controller and Host-Hub Interface PCI configuration registerslisted in order of ascending offset address. The register address map is shown in Table 6.Table 6.DRAM Controller/Host-Hub Interface Device RegisterAddress Map (Device 0) (Sheet 1 of 2)AddressOffsetRegisterSymbolRegister Name Default Value Access00–01h VID Vendor Identification 8086h RO02–03h DID Device Identification 2570h RO04–05h PCICMD PCI Command 0006h RO, R/W06–07h PCISTS PCI Status 0090h RO, R/WC08h RID Revision IdentificationSee registerdescriptionRO09h — Intel Reserved — —0Ah SUBC Sub-Class Code 00h RO0Bh BCC Base Class Code 06h RO0C — Intel Reserved — —0Dh MLT Master Latency Timer 00h RO0Eh HDR Header Type 00h RO0Fh — Intel Reserved — —10–13h APBASE Aperture Base Configuration 00000008h RO, R/W14–2Bh — Intel Reserved — —2C–2Dh SVID Subsystem Vendor Identification 0000h R/WO2E–2Fh SID Subsystem Identification 0000h R/WO30–33h — Intel Reserved — —34h CAPPTR Capabilities Pointer E4h RO35–50h — Intel Reserved — RO51h AGPM AGP Miscellaneous Configuration 00h R/W52h GC Graphics Control 0000_1000b R/W53h CSABCONT CSA Basic Control 00h RO, R/W54-5Fh — Intel Reserved — —60h FPLLCONT FPLL Clock Control 00h R/W, RO61–89h — Intel Reserved — —90h PAM0 Programmable Attribute Map 0 00h RO, R/W91h PAM1 Programmable Attribute Map 1 00h RO, R/W92h PAM2 Programmable Attribute Map 2 00h RO, R/W93h PAM3 Programmable Attribute Map 3 00h RO, R/W94h PAM4 Programmable Attribute Map 4 00h RO, R/WIntel ® 82865G/82865GV GMCH Datasheet 55
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Intel ® 865G/865GV ChipsetDatashee
Page 3: Contents1 Introduction.............
Page 6 and 7: 3.8 PCI-to-CSA Bridge Registers (De
Page 8 and 9: 5.5.3 Synchronous Display .........
Page 10 and 11: Tables1 General Terminology .......
Page 14: This page is intentionally left bla
Page 20 and 21: Introduction1.4 Intel ® 82865G GMC
Page 24: Introduction1.4.7 Display Interface
Page 27 and 28: Signal Description2.1 Host Interfac
Page 29 and 30: Signal DescriptionSignal Name Type
Page 31 and 32: Signal Description2.2.2 DDR SDRAM C
Page 33 and 34: Signal Description2.5 AGP Interface
Page 35 and 36: Signal Description2.5.4 AGP Strobes
Page 37 and 38: Signal DescriptionSignal Name Type
Page 39 and 40: Signal Description2.5.7 Intel ® DV
Page 41 and 42: Signal Description2.7 Clocks, Reset
Page 44 and 45: Signal Description2.10 GMCH Sequenc
Page 46 and 47: Signal Description2.12 Full and War
Page 48 and 49: Register DescriptionTermReservedReg
Page 50 and 51: Register Description3.3 Routing Con
Page 52 and 53: Register DescriptionIf the Bus Numb
Page 56 and 57: Register DescriptionTable 6.DRAM Co
Page 58 and 59: Register Description3.5.3 PCICMD—
Page 60 and 61: Register Description3.5.5 RID—Rev
Page 62 and 63: Register Description3.5.10 APBASE
Page 64 and 65: Register Description3.5.14 AGPM—A
Page 66 and 67: Register DescriptionNotes on Pre-Al
Page 68 and 69: Register Description3.5.17 FPLLCONT
Page 70 and 71: Register DescriptionAs an example,
Page 72 and 73: Register Description3.5.20 SMRAM—
Page 74 and 75: Register Description3.5.22 ACAPID
Page 76 and 77: Register Description3.5.24 AGPCMD
Page 78 and 79: Register Description3.5.26 APSIZE
Page 80 and 81: Register Description3.5.29 LPTT—A
Page 82 and 83: Register Description3.5.31 GMCHCFG
Page 84 and 85: Register Description3.5.32 ERRSTS
Page 86 and 87: Register Description3.5.34 SKPD—S
Page 88 and 89: Register Description3.6.1 VID1—Ve
Page 90 and 91: Register Description3.6.4 PCISTS1
Page 92 and 93: Register Description3.6.8 MLT1—Ma
Page 94 and 95: Register Description3.6.14 IOBASE1
Page 96 and 97: Register Description3.6.17 MBASE1
Page 100: Register Description3.6.22 ERRCMD1
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Register Description3.7.6 CC—Clas
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Register Description3.7.11 MMADR—
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Register Description3.7.16 CAPPOINT
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Register Description3.7.22 PMCAP—
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Register Description3.8 PCI-to-CSA
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Register Description3.8.3 PCICMD3
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Register Description3.8.5 RID3—Re
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Register Description3.8.11 SBUSN3
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Register Description3.8.15 SSTS3—
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Register Description3.8.17 MLIMIT3
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Register Description3.8.20 BCTRL3
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Register Description3.9 Overflow Co
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Register Description3.9.4 PCISTS6
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Register Description3.9.9 BAR6—Me
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Register DescriptionThe remaining 7
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Register Description3.10.3 DRT—DR
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Register DescriptionBit6:4Descripti
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System Address MapSystem Address Ma
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System Address Map4.2 Compatibility
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System Address Map4.3 Extended Memo
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System Address MapPCI Memory Addres
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Functional DescriptionFunctional De
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Functional Description5.2 System Me
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Functional Description5.2.2.1 Dynam
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Functional DescriptionTable 21. DRA
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Functional DescriptionTable 23. DRA
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Functional Description5.2.6 Configu
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Functional Description5.3.1 GMCH AG
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Functional Descriptiondown controll
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Functional Description5.3.6 Support
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Functional Description5.4.1 3D Engi
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Functional DescriptionTexture Forma
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Functional DescriptionTexture Map B
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Functional DescriptionDepth BufferT
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Functional Description5.4.3 Video E
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Functional Description5.4.5 PipesSc
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Functional DescriptionIntegrated RA
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Functional DescriptionDirect YUV fr
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Functional Description• System—
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Functional Description5.8 ClockingT
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Electrical CharacteristicsElectrica
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Electrical CharacteristicsTable 36.
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Electrical Characteristics6.5 DC Pa
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Electrical Characteristics6.6.3 DAC
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Ballout and Package InformationBall
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Ballout and Package InformationFigu
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Ballout and Package InformationTabl
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Ballout and Package Information7.2
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TestabilityTestability 8In the GMCH
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Testability8.2 XOR Chain Definition
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TestabilityTable 45. XOR Chain 1 (3
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Intel ® 82865GV GMCHIntel ® 82865
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Intel ® 82865GV GMCH9.3 Intel ® 8
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Intel ® 82865GV GMCHGMCHCFG—GMCH
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Intel ® 82865GV GMCH BalloutIntel
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Intel ® 82865GV GMCH BalloutFigure
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Intel ® 82865GV GMCH BalloutTable
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Intel ® 82865GV GMCH TestabilityIn
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Intel ® 82865GV GMCH Testability11
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Intel ® 82865GV GMCH TestabilityTa
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