Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.8.20 BCTRL3—Bridge Control Register (Device 3)Address Offset:Default Value:Access:Size:3Eh00hR/W, RO8 bitsBitDescription76Fast Back-to-Back Enable (FB2BEN)—RO. Hardwired to 0. The GMCH does not generate fastback-to-back cycles as a master on AGP.Secondary Bus reset (SREST)—RO. Hardwired to 0. The GMCH does not support generation ofreset via this bit on the AGP.Master Abort Mode (MAMODE)—RO. Hardwired to 0. This means that when acting as a master on5CSA, the GMCH will discard writes and return all 1s during reads when a master abort occurs.4 Reserved.32VGA Enable (VGAEN)—R/W. This bit control the routing of processor-initiated transactionstargeting VGA compatible I/O and memory address ranges. This bit works in conjunction with theGMCHCFG[MDAP] bit (Device 0, offset C6h) as described in Table 12.0 = Disable1 = EnableISA Enable (ISAEN)—R/W. This bit modifies the response by the GMCH to an I/O access issued bythe processor that targets ISA I/O addresses. This applies only to I/O addresses that are enabled bythe IOBASE and IOLIMIT registers.0 = Disable (default). All addresses defined by the IOBASE and IOLIMIT for processor I/Otransactions are mapped to CSA.1 = Enable. The GMCH does not forward to CSA any I/O transactions addressing the last768 bytes in each 1-KB block, even if the addresses are within the range defined by theIOBASE and IOLIMIT registers. Instead of going to CSA, these cycles are forwarded to HIwhere they can be subtractively or positively claimed by the ISA bridge.SERR Enable (SERREN)—RO. Hardwired to 0. This bit normally controls forwarding SERR# on the1 secondary interface to the primary interface. However, the GMCH does not support the SERR#signal on the CSA Bus.0 Parity Error Response Enable (PEREN)—RO. Hardwired to 0.The bit field definitions for VGAEN and MDAP are detailed in Table 12.Table 12. VGAEN and MDAP DefinitionsVGAEN MDAP Description0 0 All References to MDA and VGA space are routed to HI.0 1 Illegal combination.1 0 All VGA references are routed to this bus. MDA references are routed to HI.1 1 All VGA references are routed to this bus. MDA references are routed to HI.Intel ® 82865G/82865GV GMCH Datasheet 125