Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Intel ® 82865GV GMCH Testability11.2 XOR Chain DefinitionThe GMCH has 10 XOR chains. The XOR chain outputs are driven out on the output pins asshown in Table 56. During fullwidth testing, XOR chain outputs will be visible on both pins(For example, xor_out0 will be visible on SDM_A0 and SDM_B0). During channel shared modeon the tester, outputs will be visible on their respective channels. (For example, in channel A mode,xor_out0 will be visible on SDM_A0 and the same will be visible on SDM_B0 in channel Bmode.)Table 56. XOR Chain OutputsXOR Chain DDR Output Pin Channel A DDR Output Pin Channel Bxor_out0 SDM_A0 SDM_B0xor_out1 SDM_A1 SDM_B1xor_out2 SDM_A2 SDM_B2xor_out3 SDM_A3 SDM_B3xor_out4 SDM_A4 SDM_B4xor_out5 SDM_A5 SDM_B5xor_out6 SDM_A6 SDM_B6xor_out7 SDM_A7 SDM_B7xor_out8 HTRDY# BPRI#xor_out9 RS2# DEFER#xor_out10 RS0# RS1#xor_out11 BREQ0# CPURST#The following tables show the XOR chain pin mappings and their monitors for the GMCH.Note: Notes for Table 57 through Table 67.1. All XOR chains can be run in parallel, except chains 0 and 1, chains 0 and 2, and chains 2 and4).2. The channel A and channel B output pins for each chain show the same output.Intel ® 82865G/82865GV GMCH Datasheet 243