Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Functional DescriptionWhen the processor or the GMCH drives data, each 16-bit segment is analyzed. If more than 8 ofthe 16 signals would normally be driven low on the bus, the corresponding DINVx# signal will beasserted and the data will be inverted prior to being driven on the bus. When the processor or theGMCH receives data, it monitors DINV[3:0]# to determine if the corresponding data segmentshould be inverted.5.1.2 FSB Interrupt OverviewPentium 4 processors support FSB interrupt delivery. They do not support the APIC serial businterrupt delivery mechanism. Interrupt related messages are encoded on the FSB as “InterruptMessage Transactions.” In the 865G chipset platform FSB interrupts may originate from theprocessor on the system bus, or from a downstream device on the hub interface, or AGP. In the latercase the GMCH drives the “Interrupt Message Transaction” onto the system bus.In the 865G chipset environment the ICH5 contains IOxAPICs, and its interrupts are generated asupstream HI memory writes. Furthermore, PCI 2.3 defines MSIs (Message Signaled Interrupts)that are also in the form of memory writes. A PCI 2.3 device may generate an interrupt as an MSIcycle on its PCI bus instead of asserting a hardware signal to the IOxAPIC. The MSI may bedirected to the IOxAPIC which in turn generates an interrupt as an upstream hub interface memorywrite. Alternatively, the MSI may be directed directly to the FSB. The target of an MSI isdependent on the address of the interrupt memory write. The GMCH forwards inbound HI andAGP/PCI (PCI semantic only) memory writes to address 0FEEx_xxxxh to the FSB as “InterruptMessage Transactions.”5.1.2.1 Upstream Interrupt MessagesThe GMCH accepts message-based interrupts from PCI (PCI semantics only) hub interface andforwards them to the FSB as Interrupt Message Transactions. The interrupt messages presented tothe GMCH are in the form of memory writes to address 0FEEx_xxxxh. At the HI or PCI interface,the memory write interrupt message is treated like any other memory write; it is either posted intothe inbound data buffer (if space is available) or retried (if data buffer space is not immediatelyavailable). Once posted, the memory write from PCI or hub interface to address 0FEEx_xxxxh isdecoded as a cycle that needs to be propagated by the GMCH to the FSB as an Interrupt MessageTransaction.148 Intel ® 82865G/82865GV GMCH Datasheet