Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.25 AGPCTRL—AGP Control Register (Device 0)Address Offset:Default Value:Access:Size:B0–B3h00000000hRO, R/W32 bitsThis register provides for additional control of the AGP interface.BitDescriptions31:8 Reserved.7GTLB Enable (GTLBEN)— R/W.0 = Disable (default). The GTLB is flushed by clearing the valid bits associated with each entry. Inthis mode of operation:— All accesses that require translation bypass the GTLB— All requests that are positively decoded to the graphics aperture force the GMCH to accessthe translation table in main memory before completing the request— Valid translation table entry fetches will not be cached in the GTLB— Invalid translation table entry fetches will still be cached in the GTLB (ejecting the leastrecently used entry).1 = Enable. Normal operations of the Graphics Translation Lookaside Buffer are enabled.NOTE: This bit can be changed dynamically (i.e., while an access to GTLB occurs); however, thecompletion of the configuration write that asserts or deasserts this bit will be delayedpending a complete flush of all dirty entries from the write buffer. This delay will beincurred because this bit is used as a mechanism to signal the chipset that the graphicsaperture translation table is about to be modified or has completed modifications. In thefirst case, all dirty entries need to be flushed before the translation table is changed. In thesecond case, all dirty entries need to be flushed because one of them is likely to be atranslation table entry which must be made visible to the GTLB by flushing it to memory.6:1 Reserved.04X Override (OVER4X)—R/W. This back-door register bit allows the BIOS to force 1X mode forAGP 2.0 and 4X mode for AGP 3.0. Note that this bit must be set by the BIOS before AGPconfiguration.0 = No override1 = The RATE[2:0] bit in the AGPSTS register will be read as a 001.Intel ® 82865G/82865GV GMCH Datasheet 77