IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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Register Description3.8.8 MLT3—Master Latency Timer Register (Device 3)Address Offset:Default Value:Access:Size:0Dh00hRO, RW8 bitsThis functionality is not applicable. It is described here since these bits should be implemented as aread/write to prevent standard PCI-to-PCI bridge configuration software from getting “confused.”BitDescription7:3Scratchpad MLT (NA7:3)—R/W. These bits return the value that was last written; however, theyhave no internal function and are implemented as a Scratchpad to avoid confusing software.2:0 Reserved.3.8.9 HDR3—Header Type Register (Device 3)Address Offset:Default Value:Access:Size:0Eh01hRO8 bitsThis register identifies the header layout of the configuration space.Bit7:0DescriptionHeader Type Register (HDR)—RO.01h = GMCH Device 3 is a single function device with bridge header layout.3.8.10 PBUSN3—Primary Bus Number Register (Device 3)Address Offset:Default Value:Access:Size:18h00hRO8 bitsThis register identifies that virtual PCI-to-PCI bridge is connected to bus 0.Bit7:0DescriptionPrimary Bus Number (BUSN)—RO. Configuration software typcially programs this field with thenumber of the bus on the primary side of the bridge. Since Device 3 is an internal device and itsprimary bus is always 0, these bits are read only and are hardwired to 00h.118 Intel ® 82865G/82865GV GMCH Datasheet
Register Description3.8.11 SBUSN3—Secondary Bus Number Register (Device 3)Address Offset:Default Value:Access:Size:19h00hR/W8 bitsThis register identifies the bus number assigned to the second bus side of the virtual PCI-to-PCIbridge (i.e., CSA). This number is programmed by the PCI configuration software to allowmapping of configuration cycles to CSA.Bit7:0DescriptionSecondary Bus Number (BUSN)—R/W. This field is programmed by configuration software withthe bus number assigned to CSA.3.8.12 SMLT3—Secondary Bus Master Latency Timer Register(Device 3)Address Offset:Default Value:Access:Size:1Bh00hRO8 bitsBitDescription7:0 Reserved.Intel ® 82865G/82865GV GMCH Datasheet 119
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Intel ® 865G/865GV ChipsetDatashee
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Contents1 Introduction.............
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3.8 PCI-to-CSA Bridge Registers (De
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5.5.3 Synchronous Display .........
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Tables1 General Terminology .......
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Introduction1.4 Intel ® 82865G GMC
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Introduction1.4.7 Display Interface
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Signal Description2.1 Host Interfac
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Signal DescriptionSignal Name Type
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Signal Description2.2.2 DDR SDRAM C
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Signal Description2.5 AGP Interface
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Signal Description2.5.4 AGP Strobes
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Signal DescriptionSignal Name Type
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Signal Description2.5.7 Intel ® DV
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Signal Description2.7 Clocks, Reset
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Signal Description2.10 GMCH Sequenc
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Signal Description2.12 Full and War
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Register DescriptionTermReservedReg
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Register Description3.3 Routing Con
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Register DescriptionIf the Bus Numb
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Register Description3.4.2 CONFIG_DA
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Register DescriptionTable 6.DRAM Co
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Register Description3.5.3 PCICMD—
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Register Description3.5.5 RID—Rev
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Register Description3.5.10 APBASE
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Register Description3.5.14 AGPM—A
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Register DescriptionNotes on Pre-Al
Page 68 and 69: Register Description3.5.17 FPLLCONT
Page 70 and 71: Register DescriptionAs an example,
Page 72 and 73: Register Description3.5.20 SMRAM—
Page 74 and 75: Register Description3.5.22 ACAPID
Page 76 and 77: Register Description3.5.24 AGPCMD
Page 78 and 79: Register Description3.5.26 APSIZE
Page 80 and 81: Register Description3.5.29 LPTT—A
Page 82 and 83: Register Description3.5.31 GMCHCFG
Page 84 and 85: Register Description3.5.32 ERRSTS
Page 86 and 87: Register Description3.5.34 SKPD—S
Page 88 and 89: Register Description3.6.1 VID1—Ve
Page 90 and 91: Register Description3.6.4 PCISTS1
Page 92 and 93: Register Description3.6.8 MLT1—Ma
Page 94 and 95: Register Description3.6.14 IOBASE1
Page 96 and 97: Register Description3.6.17 MBASE1
Page 100: Register Description3.6.22 ERRCMD1
Page 105 and 106: Register Description3.7.6 CC—Clas
Page 107 and 108: Register Description3.7.11 MMADR—
Page 109 and 110: Register Description3.7.16 CAPPOINT
Page 111 and 112: Register Description3.7.22 PMCAP—
Page 113 and 114: Register Description3.8 PCI-to-CSA
Page 115 and 116: Register Description3.8.3 PCICMD3
Page 117: Register Description3.8.5 RID3—Re
Page 121 and 122: Register Description3.8.15 SSTS3—
Page 123 and 124: Register Description3.8.17 MLIMIT3
Page 125 and 126: Register Description3.8.20 BCTRL3
Page 127 and 128: Register Description3.9 Overflow Co
Page 129 and 130: Register Description3.9.4 PCISTS6
Page 131 and 132: Register Description3.9.9 BAR6—Me
Page 133 and 134: Register DescriptionThe remaining 7
Page 135 and 136: Register Description3.10.3 DRT—DR
Page 137 and 138: Register DescriptionBit6:4Descripti
Page 139 and 140: System Address MapSystem Address Ma
Page 141 and 142: System Address Map4.2 Compatibility
Page 143 and 144: System Address Map4.3 Extended Memo
Page 145 and 146: System Address MapPCI Memory Addres
Page 147 and 148: Functional DescriptionFunctional De
Page 149 and 150: Functional Description5.2 System Me
Page 151 and 152: Functional Description5.2.2.1 Dynam
Page 153 and 154: Functional DescriptionTable 21. DRA
Page 155 and 156: Functional DescriptionTable 23. DRA
Page 157 and 158: Functional Description5.2.6 Configu
Page 159 and 160: Functional Description5.3.1 GMCH AG
Page 161 and 162: Functional Descriptiondown controll
Page 163 and 164: Functional Description5.3.6 Support
Page 165 and 166: Functional Description5.4.1 3D Engi
Page 167 and 168: Functional DescriptionTexture Forma
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Functional DescriptionTexture Map B
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Functional DescriptionDepth BufferT
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Functional Description5.4.3 Video E
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Functional Description5.4.5 PipesSc
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Functional DescriptionIntegrated RA
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Functional DescriptionDirect YUV fr
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Functional Description• System—
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Functional Description5.8 ClockingT
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Electrical CharacteristicsElectrica
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Electrical CharacteristicsTable 36.
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Electrical Characteristics6.5 DC Pa
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Electrical Characteristics6.6.3 DAC
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Ballout and Package InformationBall
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Ballout and Package InformationFigu
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Ballout and Package InformationTabl
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Ballout and Package Information7.2
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TestabilityTestability 8In the GMCH
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Testability8.2 XOR Chain Definition
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TestabilityTable 45. XOR Chain 1 (3
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Intel ® 82865GV GMCHIntel ® 82865
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Intel ® 82865GV GMCH9.3 Intel ® 8
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Intel ® 82865GV GMCHGMCHCFG—GMCH
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Intel ® 82865GV GMCH BalloutIntel
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Intel ® 82865GV GMCH BalloutFigure
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Intel ® 82865GV GMCH BalloutTable
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Intel ® 82865GV GMCH TestabilityIn
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Intel ® 82865GV GMCH Testability11
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Intel ® 82865GV GMCH TestabilityTa
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IntelÂ® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

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