Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.22 ACAPID—AGP Capability Identifier Register (Device 0)Address Offset:Default Value:Access:Size:A0h–A3h00300002hRO32 bitsThis register provides standard identifier for AGP capability.BitDescriptions31:24 Reserved.23:2019:1615:87:0Major AGP Revision Number (MAJREV)—RO. These bits provide a major revision number ofAGP specification to which this version of GMCH conforms. This field is hardwired to value of0011b (i.e., implying Rev 3.x).Minor AGP Revision Number (MINREV)—RO. These bits provide a minor revision number ofAGP specification to which this version of GMCH conforms. This number is hardwired to value of0000 which implies that the revision is x.0. Together with major revision number this field identifiesthe GMCH as an AGP Rev 3.0 compliant device.Next Capability Pointer (NCAPTR)—RO. AGP capability is the first and the last capabilitydescribed via the capability pointer mechanism and therefore these bits are hardwired to 0 toindicate the end of the capability linked list.AGP Capability ID (CAPID)—RO. This field identifies the linked list item as containing AGPregisters. This field has a value of 0000_0010b assigned by the PCI SIG.3.5.23 AGPSTAT—AGP Status Register (Device 0)Address Offset:Default Value:Access:Size:A4–A7h1F004217h in AGP 2.0 mode1F004A13h in AGP 3.0 modeRO32 bitsThis register reports AGP device capability/status.Bit31:24DescriptionsRequest Queue (RQ)—RO. Hardwired to 1Fh to indicate that a maximum of 32 outstanding AGPcommand requests can be handled by the GMCH. This field contains the maximum number ofAGP command requests the GMCH is configured to manage.23:16 Reserved.15:1312:10ARQSZ—RO. This field is LOG2 of the optimum asynchronous request size in bytes minus 4 to beused with the target. The master should attempt to issue a group of sequential back-to-backasynchronous requests that total to this size and for which the group is naturally aligned.Optimum_request_size = 2 ^ (ARQSZ+4).Hardwired to 010 to indicate 64 BCAL_Cycle—RO. This field specifies the required period for GMCH initiated bus cycle forcalibrating I/O buffers. Hardwired to 010, indicating 64 ms.Side Band Addressing Support (SBA)—RO. Hardwired to 1, indicating that the GMCH supports9side band addressing.8:6 Reserved.5Greater Than Four Gigabyte Support (GT4GIG)—RO. Hardwired to 0, indicating that the GMCHdoes not support addresses greater than 4 GB.74 Intel ® 82865G/82865GV GMCH Datasheet