Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.6.11 SBUSN1—Secondary Bus Number Register (Device 1)Address Offset:Default Value:Access:Size:19h00hR/W8 bitsThis register identifies the bus number assigned to the second bus side of the virtual PCI-to-PCIbridge (i.e., to PCI_B/AGP). This number is programmed by the PCI configuration software toallow mapping of configuration cycles to PCI_B/AGP.Bit7:0DescriptionsSecondary Bus Number (SBUSN)—RO. This field is programmed by configuration software withthe bus number assigned to PCI_B.3.6.12 SUBUSN1—Subordinate Bus Number Register (Device 1)Address Offset:Default Value:Access:Size:1Ah00hR/W8 bitsThis register identifies the subordinate bus (if any) that resides at the level below PCI_B/AGP. Thisnumber is programmed by the PCI configuration software to allow mapping of configurationcycles to PCI_B/AGP.Bit7:0DescriptionsSubordinate Bus Number (BUSN)—R/W. This register is programmed by configuration softwarewith the number of the highest subordinate bus that lies behind the Device 1 bridge. When only asingle PCI device resides on the AGP/PCI_B segment, this register will contain the same value asthe SBUSN1 register.3.6.13 SMLT1—Secondary Bus Master Latency Timer Register(Device 1)Address Offset:Default Value:Access:Size:1Bh00hRO, R/W8 bitsThis register control the bus tenure of the GMCH on AGP/PCI the same way Device 0 MLTcontrols the access to the PCI_A bus.BitDescriptions7:3 Secondary MLT Counter Value (MLT)—R/W. Programmable, default = 0 (SMLT disabled)2:0 Reserved.Intel ® 82865G/82865GV GMCH Datasheet 93