Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register DescriptionELSE defaults to Hub Interface.VGA IO space decode to IGD:IF IGE = 1 AND IVD = 0 AND Device 2 IO_Access_En = 1 AND Device 2 in Powered up D0state AND →Additional qualification within IGD decode (comprehends MDA requirements).IO Access MSRb03CX 3DX 3B0h–3BBh 3BCh–3BFh0 IGDELSE VGA IO space Legacy Decode:IF Device 1 IO_Access_En = 1.PCI-to-PCI Bridgeor Hub Interface1 IGD IGDIGDPCI-to-PCI Bridgeor Hub InterfacePCI-to-PCI Bridgeor Hub InterfacePCI-to-PCI Bridgeor Hub InterfaceVGA I/OMDA I/Ox3B0h – x3BBh and x3C0h – x3DFhx3B4h, x3B5h, x3B8h, x3B9h, x3BAh, x3BFhVGA_EN MDAP Range Destination Exceptions/Notes0 0 VGA, MDA Hub Interfacex3BCh – x3BFh goes to AGP if ISA enabled bit isnot set in Device 10 1 Illegal Illegal Illegal1 0 VGA AGP Non-VGA Ranges will also go to Hub Interface1 1 VGA, MDAELSE defaults to Hub Interface.AGPHub Interfacex3BCh – x3BEh will also go to Hub Interface3.5.16 CSABCONT—CSA Basic Control Register (Device 0)Address Offset:Default:Access:Size:53h00hR/W, RO8 bitsBitDescription7:1 Reserved.0Device Not Present bit—R/W.0 = Device Not Enabled1 = Device EnabledIntel ® 82865G/82865GV GMCH Datasheet 67