Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.5.28 AMTT—AGP MTT Control Register (Device 0)Address Offset:Default Value:Access:Size:BCh10hRO, R/W8 bitsAMTT is an 8-bit register that controls the amount of time that the GMCH’s arbiter allows AGP/PCI master to perform multiple back-to-back transactions. The GMCH's AMTT mechanism is usedto optimize the performance of the AGP master (using PCI semantics) that performs multiple backto-backtransactions to fragmented memory ranges (and as a consequence it can not use long bursttransfers). The AMTT mechanism applies to the Processor-AGP/PCI transactions as well and itassures the processor of a fair share of the AGP/PCI interface bandwidth.The number of clocks programmed in the AMTT represents the guaranteed time slice (measured in66 MHz clocks) allotted to the current agent (either AGP/PCI master or Host bridge) after whichthe AGP arbiter will grant the bus to another agent. The default value of AMTT is 00h and disablesthis function. The AMTT value can be programmed with 8-clock granularity. For example, if theAMTT is programmed to 18h, then the selected value corresponds to the time period of 24 AGP(66 MHz) clocks. Set by BIOS.Bit7:3DescriptionsMulti-Transaction Timer Count Value (MTTC)—R/W. The number programmed into these bitsrepresents the time slice (measured in eight, 66 MHz clock granularity) allotted to the current agent(either AGP/PCI master or Host bridge) after which the AGP arbiter will grant the bus to anotheragent.2:0 Reserved.Intel ® 82865G/82865GV GMCH Datasheet 79