Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

TestabilityTestability 8In the GMCH, testability for Automated Test Equipment (ATE) board level testing has beenimplemented as an XOR chain. An XOR-tree is a chain of XOR gates, each with one input pinconnected to it.8.1 XOR Test Mode InitializationXOR test mode can be entered by driving GSBA6#, GSBA7#, TESTIN#, PWROK low, andRSTIN# low, then driving PWROK high, then RSTIN# high. XOR test mode via TESTIN# doesnot require a clock. But toggling of HCLKP and HCLKN as shown in Figure 20 is required fordeterministic XOR operation when in AGP 2.0 mode. If the component is in AGP 3.0 mode,GSBA6#, GSBA7#, and GC#/BE1 must be driven high.Figure 20. XOR Toggling of HCLKP and HCLKNPWROK1 msTESTIN#GSBA6GFRAME#RSTIN#GCLKINHCLKPHCLKNDREFCLKPin testing will not start until RSTIN# is deasserted. Figure 21 shows chains that are testedsequentially. Note that for the GMCH, sequential testing is not required. All chains can be tested inparallel for test time reduction.Intel ® 82865G/82865GV GMCH Datasheet 211