Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Signal DescriptionSignal Name Type DescriptionGC/BE[3:0]# (2.0)GC#/BE[3:0] (3.0)GPAR/ADD_DETECTDBI_LO(3.0 only)I/OAGPI/OAGPI/OAGPCommand/Byte Enables: These signals provide the command during theaddress phase of a GFRAME(#) or GPIPE(#) transaction and byte enablesduring data phases. Byte enables are not used for read data of AGP 1X and2X and 4X and 8X reads. These signals operate at the same data rate as theGAD[31:0] signals at any given time.Parity: GPAR is not used on AGP transactions. It is used during GFRAME(#)based transactions as defined by the PCI specification. GPAR is not usedduring fast writes.Add Detect: The GMCH multiplexes an ADD_DETECT signal with the GPARsignal on the AGP bus. This signal acts as a strap and indicates whether theinterface is in AGP or DVO mode. The GMCH has an internal pull-up on thissignal that will naturally pull it high. If an ADD card is present, the signal will bepulled low on the ADD card and the AGP/DVO multiplex select bit in theGMCHCFG register will be set to DVO mode. Motherboards that do not use anAGP connector should have a pull-down resistor on ADD_DETECT if theyhave digital display devices connected to the interface.Dynamic Bus Inversion LO: This AGP 3.0 only signal goes along withGAD[15:0] to indicate whether GAD[15:0] must be inverted on the receivingend.• DBI_LO= 0: GAD[15:0] are not inverted so receiver may use as is.• DBI_LO= 1: GAD[15:0] are inverted so receiver must invert before use.The GADSTBF1 and GADSTBS1 strobes are used with the DBI_LO. Dynamicbus inversion is used in AGP 3.0 signaling mode only.NOTES:1. PCIRST# from the ICH5 is connected to RSTIN# and is used to reset AGP interface logic in the GMCH. TheAGP agent will also typically use PCIRST# provided by the ICH5 as an input to reset its internal logic.2. LOCK# signal is not supported on the AGP interface (even for PCI operations).3. The term (2.0) following a signal name indicates its function in AGP 2.0 signaling mode (1.5 V swing).4. The term (3.0) following a signal name indicates its function in AGP 3.0 signaling mode (0.8 V swing).2.5.5.1 PCI Pins during PCI Transactions on AGP InterfacePCI signals described in a previous table behave according to PCI 2.1 specifications when used toperform PCI transactions on the AGP interface.2.5.6 Multiplexed Intel ® DVOs on AGPThe following signals are multiplexed on the AGP signals.Signal Name Type DescriptionDVOB_CLK;DVOB_CLK#DVOB_D[11:0]DVOB_HSYNCDVOB_VSYNCDVOB_BLANK#OAGPOAGPOAGPOAGPOAGPDVOB Clock Output: These pins provide a differential pair reference clockthat can run up to 165 MHz. Care should be taken to be sure that DVOB_CLKis connected to the primary clock receiver of the Intel ® DVO device.DVOB Data: This data bus is used to drive 12-bit pixel data on each edge ofDVOB_CLK(#). This provides 24-bits of data per clock.Horizontal Sync: HSYNC signal for the DVOB interface. The active polarityof the signal is programmable.Vertical Sync: VSYNC signal for the DVOB interface. The active polarity ofthe signal is programmable.Flicker Blank or Border Period Indication: DVOB_BLANK# is aprogrammable output pin driven by the GMCH. When programmed as a blankperiod indication, this pin indicates active pixels excluding the border. Whenprogrammed as a border period indication, this pin indicates active pixelincluding the border pixels.Intel ® 82865G/82865GV GMCH Datasheet 37