Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.8.16 MBASE3—Memory Base Address Register (Device 3)Address Offset: 20–21hDefault Value: FFF0hAccess:RO, RWSize:16 bitsThis register controls the processor-to-CSA non-prefetchable memory access routing based on thefollowing formula:MEMORY_BASE ≤ address ≤ MEMORY_LIMITThe Upper 12 bits of the register are read/write and correspond to the upper 12 address bitsA[31:20] of the 32-bit address. The bottom 4 bits of this register are read only and return zeroeswhen read. This register must be initialized by the configuration software. For the purpose ofaddress decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memoryaddress range will be aligned to 1-MB boundary.BitDescription15:4Memory Address Limit (MLIMIT)— R/W. This field corresponds to A[31:20] of the lower limit ofthe memory range that will be passed by Device 3 bridge to CSA.3:0 Reserved.122 Intel ® 82865G/82865GV GMCH Datasheet