Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Register Description3.8.3 PCICMD3—PCI Command Register (Device 3)Address Offset:Default:Access:Size:04h−05h0000hRO, R/W16 bitsBitDescription15:10 Reserved.9 Fast Back-to-Back (FB2B)⎯RO. Hardwired to 0.SERR# Enable (SERRE) ⎯R/W. This bit is a global enable bit for Device 3 SERR messaging. TheGMCH communicates the SERR# condition by sending a SERR message to the ICH5.8 0 = Disable. The SERR message is not generated by the GMCH for Device 3.1 = Enable. The GMCH is enabled to generate SERR messages over HI for specific Device 3error conditions that are individually enabled in the BCTRL3 register. The error status isreported in the PCISTS3 register.7 Address/Data Stepping (ADSTEP)⎯RO. Hardwired to 0.Parity Error Enable (PERRE) ⎯RO. Hardwired to 0. Parity checking is not supported on the6primary side of this device.5 Reserved.4 Memory Write and Invalidate Enable (MWIE)⎯RO. Hardwired to 0.3 Special Cycle Enable (SCE)⎯RO. Hardwired to 0.210Bus Master Enable (BME)⎯R/W. This bit is not functional. It is a R/W bit for compatibility withcompliance testing software.Memory Access Enable (MAE)⎯R/W. This bit must be set to 1 to enable the memory and prefetchablememory address ranges defined in the MBASE3, MLIMIT3, PMBASE3, and PMLIMIT3registers.0 = Disable (default).1 = Enable.I/O Access Enable (IOAE)⎯R/W. This bit must be set to 1 to enable the I/O address rangedefined in the IOBASE3 and IOLIMIT3 registers0 = Disable (default).1 = Enable.Intel ® 82865G/82865GV GMCH Datasheet 115