Intel® 865G/865GV Chipset Datasheet - download.intel.nl - Intel

Introduction1.4 Intel ® 82865G GMCH OverviewThe GMCH provides the host bridge interfaces and has an integrated graphics device with displayinterfaces. The GMCH contains advanced desktop power management logic.The GMCH’s role in a system is to provide high performance integrated graphics and manage theflow of information between its six interfaces: the processor front side bus (FSB), the memoryattached to the SDRAM controller, the AGP 3.0 port, the hub interface, CSA interface, and displayinterfaces. This includes arbitrating between the six interfaces when each initiates an operation.While doing so, the GMCH supports data coherency via snooping and performs address translationfor accesses to the AGP aperture memory. To increase system performance, the GMCHincorporates several queues and a write cache.1.4.1 Host InterfaceThe GMCH supports a single, Pentium 4 processor with 512-KB L2 cache on 0.13 micron process.The processor interface supports the Pentium 4 processor subset of the Extended Mode of theScalable Bus Protocol. The GMCH supports FSB frequencies of 400/533/800 MHz(100 MHz, 133 MHz, and 200 MHz HCLK, respectively) using a scalable FSB VCC_CPU. Itsupports 32-bit host addressing, decoding up to 4 GB of the processor’s memory address space.Host-initiated I/O cycles are decoded to AGP/PCI_B, Hub Interface, or the GMCH configurationspace. Host-initiated memory cycles are decoded to AGP/PCI_B, Hub Interface or system memory.All memory accesses from the host interface that hit the graphics aperture are translated using anAGP address translation table. AGP/PCI_B device accesses to non-cacheable system memory arenot snooped on the host bus. Memory accesses initiated from AGP/PCI_B using PCI semantics andfrom hub interface to system SDRAM will be snooped on the host bus.1.4.2 System Memory InterfaceThe GMCH integrates a system memory DDR controller with two, 64-bit wide interfaces (up totwo channels of DDR). Only Double Data Rate (DDR) SDRAM memory is supported; thus, thebuffers support only SSTL_2 signal interfaces. The memory controller interface is fullyconfigurable through a set of control registers.System Memory Interface• Supports one or two 64-bit wide DDR data channels• Available bandwidth up to 3.2 GB/s (DDR400) for single-channel mode and 6.4 GB/s(DDR400) in dual-channel mode.• Support for non ECC DIMMs• Supports 128-Mb, 256-Mb, 512-Mb DDR technologies• Supports only x8, x16, DDR devices with 4-banks• Registered DIMMs not supported• Supports opportunistic refresh• Up to 16 simultaneously open pages (four per row, four rows maximum)• SPD (Serial Presence Detect) scheme for DIMM detection support• Suspend-to-RAM support using CKE• Supports configurations defined in the JEDEC DDR1 DIMM specification only20 Intel ® 82865G/82865GV GMCH Datasheet