Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

R
HOSTCLK
HOSTMIIMSEL
HOSTREQ
HOSTOPCODE[1:0]
HOSTADDR[9:0]
HOSTWRDATA[15:0]
HOSTMIIMRDY
HOSTRDDATA[15:0]
HOSTEMAC1SEL
Using the DCR Bus
Using the DCR Bus
As noted in Figure 4-7, if a read transaction is initiated, the HOSTRDDATA bus is valid at the
point indicated. If a write transaction is initiated, the HOSTWRDATA bus must be valid at the
point indicated. The bus is locked until the transfer completes.
The DCREMACENABLE signal selects between the DCR bus or the host bus during the FPGA
power-up configuration. To access the host interface through the DCR bus, the
DCREMACENABLE signal must be asserted by tying the signal High in the FPGA logic.
The address space available on the DCR bus is limited. The host interface is accessed
indirectly using only four registers per EMAC in the DCR address space. Accessing the
host interface though the DCR bus requires more software complexity than though the
host bus. For further information, see the example software routines in “Interfacing to a
Processor,” page 107.
When the DCR bus is used to access the internal registers of the Ethernet MAC, the DCR
bus bridge in the host interface translates commands carried over the DCR bus into
Ethernet MAC host bus signals. These signals then configure one of the Ethernet MACs.
Clocking Requirements
Figure 4-7: MDIO Access Through the Host Bus
UG194_4_07_100708
The HOSTCLK frequency must be an integer divide of the DCR clock frequency, and the
two clocks must be phase-aligned.
TEMAC User Guide www.xilinx.com 101
UG194 (v1.10) February 14, 2011