Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Client Interface
Chapter 3
This chapter provides useful design information for the Virtex®-5 Ethernet MAC. It
contains the following sections:
“Transmit (TX) Client: 8-Bit Interface (without Clock Enables)”
“Transmit (TX) Client: 8-Bit Interface (with Clock Enables)”
“Transmit (TX) Client: 16-Bit Interface”
“Receive (RX) Client: 8-Bit Interface (without Clock Enables)”
“Receive (RX) Client: 8-Bit Interface (with Clock Enables)”
“Receive (RX) Client: 16-Bit Interface”
“Address Filtering”
“Flow Control Block”
“Statistics Vectors”
The client interface is designed for maximum flexibility for matching the client switching
logic or network processor interface.
The transmit and receive client interfaces can be configured to handle either 8-bit data
transfers or 16-bit data transfers, where the default is 8 bits.
The 8-bit client operation supports all physical interfaces and is offered in two alterative
clocking modes: the standard clocking scheme without clock enables or an alternative
clock enable scheme. “Ethernet MAC Clocks,” page 205 introduces these two clocking
models and describes how the clock enable scheme can be used to reduce the number of
global clock buffers required for the design. Table 2-1, page 30 illustrates the physical
interface configurations that can use the advanced clock enable scheme.
The 16-bit client operation is enabled by setting the EMAC#_RX16BITCLIENT_ENABLE
and EMAC#_TX16BITCLIENT_ENABLE attributes to TRUE. This mode of operation is
only available with the 1000BASE-X PCS/PMA physical interface. Using this scheme, the
Ethernet MAC can be over-clocked to provide operation above 1 Gb/s. “16-Bit Data
Client,” page 170 provides a description of the clocking scheme for this mode.
TEMAC User Guide www.xilinx.com 51
UG194 (v1.10) February 14, 2011