Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 5: MDIO Interface Table 5-19: SGMII Auto-Negotiation Link Partner Ability Base Register (Register 5) (Cont’d) Bit(s) Name Description Type Default Value 5.11:10 Speed The resolved operating speed that the external PHY device has auto-negotiated with its link partner across the PHY link (see Figure 5-8). 00 = 10 Mb/s. 01 = 100 Mb/s. 10 = 1000 Mb/s. 11 = Reserved. Read only 00 5.9:1 Reserved Always returns 0s. Returns 0s 000000000 5.0 Reserved Always returns 1. Returns 1 1 Table 5-20: SGMII Auto-Negotiation Expansion Register (Register 6) Bit(s) Name Description Type Default Value 6.15:3 Reserved Always returns 0s. Returns 0s 0000000000000 6.2 Next Page Able The Ethernet MAC always returns a 1 for this bit because the device is Next Page Able. 6.1 Page Received 1 = A new page is received. 0 = A new page is not received. Returns 1 1 Read only. Self clearing on read. 6.0 Reserved Always returns 0s. Returns 0s 0000000 Table 5-21: SGMII Auto-Negotiation Next Page Transmit Register (Register 7) Bit(s) Name Description Type Default Value 7.15 Next Page 1 = Additional next page(s) will follow 0 = Last page. Read/Write 0 7.14 Reserved Always returns 0. Returns 0 0 7.13 Message Page 1 = Message Page. 0 = Unformatted Page. 7.12 Acknowledge 2 1 = Complies with message. 0 = Cannot comply with message. Read/Write 1 Read/Write 0 7.11 Toggle Value toggles between subsequent pages. Read Only 0 7.10:0 Message or Unformatted Code Field Message code field or unformatted page encoding as dictated by 7.13. Table 5-22: SGMII Auto-Negotiation Next Page Receive Register (Register 8) Read/Write 00000000001 (Null Message Code) Bit(s) Name Description Type Default Value 8.15 Next Page 1 = Additional Next Page(s) will follow. 0 = Last page. 8.14 Acknowledge Used by Auto-Negotiation function to indicate reception of a link partner’s base or next page. 8.13 Message Page 1 = Message Page. 0 = Unformatted Page. Read Only 0 Read Only 0 Read Only 0 134 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 0 R
R Table 5-22: SGMII Auto-Negotiation Next Page Receive Register (Register 8) (Cont’d) 8.12 Acknowledge 2 1 = Complies with message. 0 = Cannot comply with message. SGMII Management Registers Bit(s) Name Description Type Default Value Read Only 0 8.11 Toggle Value toggles between subsequent next pages. Read Only 0 8.10:0 Message / Unformatted Code Field Message code field or unformatted page encoding as dictated by 8.13. Table 5-23: SGMII Extended Status Register (Register 15) Read Only 00000000000 Bit(s) Name Description Type Default Value 15.15 1000BASE-X Full Duplex 15.14 1000BASE-X Half Duplex 15.13 1000BASE-T Full Duplex 15.12 1000BASE-T Half Duplex The Ethernet MAC always returns a 1 for this bit because 1000BASE-X full duplex is supported. The Ethernet MAC always returns a 0 for this bit because 1000BASE-X half duplex is not supported. The Ethernet MAC always returns a 0 for this bit because 1000BASE-T full duplex is not supported. The Ethernet MAC always returns a 0 for this bit because 1000BASE-T half duplex is not supported. Returns 1 1 Returns 0 0 Returns 0 0 Returns 0 0 15.11:0 Reserved Always returns 0s. Returns 0s 000000000000 Table 5-24: SGMII Vendor-Specific Register: Auto-Negotiation Interrupt Control Register (Register 16) Bit(s) Name Description Type Default Value 16.15:2 Reserved Always returns 0s. Returns 0s 00000000000000 16.1 Interrupt Status 1 = Interrupt is asserted. 0 = Interrupt is not asserted. If the interrupt is enabled, this bit is set upon the completion of an auto-negotiation cycle. Writing 0 to this bit is the only way to clear it. If the interrupt is disabled, this bit is cleared to 0. The EMAC#CLIENTANINTERRUPT port is wired to this bit. 16.0 Interrupt Enable 1 = Interrupt is enabled. 0 = Interrupt is disabled. Read/Write 0 Read/Write 1 TEMAC User Guide www.xilinx.com 135 UG194 (v1.10) February 14, 2011
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133: 1.2 SGMII Link Status R Table 5-16:
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180: FPGA R Introduction to the SGMII Im
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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