Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 2: Ethernet MAC Overview
Table 2-15: CLIENTEMAC#DCMLOCKED Signal
Signal Direction Description
CLIENTEMAC#DCMLOCKED Input If a DCM is used to derive any of the clock signals, the LOCKED
port of the DCM must be connected to the
CLIENTEMAC#DCMLOCKED port. The Ethernet MAC is held in reset
until CLIENTEMAC#DCMLOCKED is asserted High. If the RocketIO
serial transceiver PLL is used, the PLLLKDET signal should be
ANDed with the DCM LOCK signal.
If a DCM is not used, both CLIENTEMAC#DCMLOCKED ports from
EMAC0 and EMAC 1 must be tied High.
If any Ethernet MAC is not used, CLIENTEMAC#DCMLOCKED must be
tied to High.
Ethernet MAC Attributes
This section describes the attributes (control parameters) that are used to configure the
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC. Some of these attributes control the
static configuration of the Ethernet MAC and others are used to preconfigure the internal
control registers. The values of these attributes are loaded into the Ethernet MAC at powerup
or when the Ethernet MAC is reset (1) .
The attributes are divided into five sections: mode configuration, MAC configuration,
physical interface, address filter, and DCR base address attributes.
The mode configuration attributes control the static behavior of the Ethernet MAC,
including whether the Ethernet MAC has a host interface, the type of physical interface,
the width of the client interface and whether the MDIO interface is enabled. These
attributes are not dynamically reconfigurable.
All other attributes described in Table 2-16 (unless stated otherwise) define default values
for internal registers. If the host interface is not enabled on the Ethernet MAC, these
attributes allow the user to set the internal control register defaults. If the host interface is
enabled (by setting the EMAC#_HOST_ENABLE attribute to be TRUE), then the host
interface can be used to dynamically change the associated register contents or to read the
register contents.
1. An attribute value of TRUE is translated into a bit value of 1; a value of FALSE equals a bit value of 0.
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UG194 (v1.10) February 14, 2011
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