Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 2: Ethernet MAC Overview Table 2-11: RocketIO Serial Transceiver Connections Signal Direction Description EMAC#PHYENCOMMAALIGN Output Enable RocketIO serial transceiver PMA layer to realign to commas. EMAC#PHYLOOPBACKMSB Output Perform loopback testing in the RocketIO serial transceiver from TX to RX. EMAC#PHYMGTRXRESET Output Reset to RocketIO serial transceiver RXRESET. EMAC#PHYMGTTXRESET Output Reset to RocketIO serial transceiver TXRESET. EMAC#PHYPOWERDOWN Output Power-down the RocketIO serial transceiver. EMAC#PHYSYNCACQSTATUS Output The output from the receiver’s synchronization state machine of IEEE Std 802.3, clause 36. When asserted High, the received bitstream is synchronized. The state machine is in one of the SYNC_ACQUIRED states of IEEE Std 802.3, figures 36-39. When deasserted Low, no synchronization has been obtained. EMAC#PHYTXCHARDISPMODE Output Set running disparity for current byte. EMAC#PHYTXCHARDISPVAL Output Set running disparity value. EMAC#PHYTXCHARISK Output K character transmitted in TXDATA. PHYEMAC#RXBUFSTATUS[1:0] Input Receiver Elastic Buffer Status: Bit 1 asserted indicates overflow or underflow. PHYEMAC#RXCHARISCOMMA Input Comma detected in RXDATA. PHYEMAC#RXCHARISK Input K character received or extra data bit in RXDATA. When RXNOTINTABLE is asserted, this signal becomes the tenth bit in RXDATA. PHYEMAC#RXCHECKINGCRC Input Reserved - tied to GND. PHYEMAC#RXBUFERR Input Reserved - tied to GND. PHYEMAC#RXCOMMADET Input Reserved - tied to GND. PHYEMAC#RXDISPERR Input Disparity error in RXDATA. PHYEMAC#RXLOSSOFSYNC[1:0] Input Reserved - tied to GND. PHYEMAC#RXNOTINTABLE Input Indicates non-existent 8B/10 code. PHYEMAC#RXRUNDISP Input Running disparity in the received serial data. When RXNOTINTABLE is asserted in RXDATA, this signal becomes the ninth data bit. PHYEMAC#RXCLKCORCNT[2:0] Input Status showing the occurrence of a clock correction. PHYEMAC#TXBUFERR Input TX buffer error (overflow or underflow). 40 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Table 2-12: PCS/PMA Signals Table 2-12 shows the PCS/PMA signals. Signal Direction Description Global Clock and Reset Signals Global Clock Signal < Table 2-13: Global Clock Signals Ethernet MAC Signal Descriptions PHYEMAC#PHYAD[4:0] Input Physical interface address of MDIO register set for the PCS sublayer. PHYEMAC#SIGNALDET Input Signal direct from PMD sublayer indicating the presence of light detected at the optical receiver, as defined in IEEE Std 802.3, clause 36. If asserted High, the optical receiver has detected light. If deasserted Low, indicates the absence of light. If unused, this signal should be tied High for correct operation. EMAC#CLIENTANINTERRUPT Output Interrupt upon auto-negotiation. Table 2-13 shows the global clock signal that is necessary for most configurations of the Virtex-5 FPGA Ethernet MAC. See Appendix B, “Ethernet MAC Clocks” for further details. Signal Direction Description PHYEMAC#GTXCLK Input Clock supplied by the user to derive the other transmit clocks. Clock tolerance must be within the IEEE Std 802.3-2002 specification. Reset Signal Table 2-14: Reset Signal Table 2-14 describes the Reset signal. Signal Direction Description Reset Input Asynchronous reset of the entire Ethernet MAC. CLIENTEMAC#DCMLOCKED Signal Table 2-15 describes the CLIENTEMAC#DCMLOCKED signal. TEMAC User Guide www.xilinx.com 41 UG194 (v1.10) February 14, 2011
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39: R Table 2-8: PHY Data and Control S
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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