Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 3: Client Interface
Attributes,” page 42 describes the EMAC#_USECLKEN attribute, which is set to TRUE for
this configuration.
In this mode, the client interface is synchronous to the physical interface clock. This
configuration reduces the number of BUFGs that are used to implement the Ethernet MAC
design. See “Ethernet MAC Clocks,” page 205 for some general information on this
clocking scheme. More details are available for specific physical interface configurations in
the following sections:
“MII Clock Management using Clock Enables”
“GMII Clock Management for Tri-Speed Operation Using Clock Enables”
“RGMII Clock Management for Tri-Speed Operation Using Clock Enables”
For the receive interface, the PHYEMAC#RXCLK signal is used as the clock, and the
EMAC#CLIENTRXCLIENTCLKOUT signal is used as the clock enable.
Figure 3-19 shows the timing of a normal inbound frame transfer at 1 Gb/s. Data is
transferred to the client on the rising edge of PHYEMAC#RXCLK. The output clock enable,
EMAC#CLIENTRXCLIENTCLKOUT, is held High.
PHYEMAC#RXCLK
EMAC#CLIENTRXCLIENTCLKOUT
EMAC#CLIENTRXD[7:0]
EMAC#CLIENTRXDVLD
EMAC#CLIENTRXGOODFRAME
EMAC#CLIENTRXBADFRAME
DA SA L/T DATA
UG194_3_19_072106
Figure 3-19: Normal Frame Reception at 1 Gb/s with EMAC#_USECLKEN Set to TRUE
Figure 3-20 shows the reception of a frame at speeds below 1 Gb/s. The physical interface
clock runs at twice the speed of the client interface clock and so the output clock enable,
EMAC#CLIENTRXCLIENTCLKOUT, is only asserted on every second cycle of
68 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
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