Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Using the DCR Bus
The IRENABLE_e# register is programmed to allow updating of the interrupt request in
the IRSTATUS_e# register. When an enable bit is cleared, the corresponding bit in the
IRSTATUS_e# register is not updated.
Table 4-22: Host Interface MDIO Write Data Register (MIIMWRDATA)
Address Code
0x3B0
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Interfacing to a Processor
DCR Interrupts
RESERVED MIIMWRDATA
Bit Description Default Value
[0:15] Reserved. All 0s
[16:31] Data. Temporarily holds MDIO write data for output onto the host write data bus. Undefined
The DCR bridge ignores any new DCR command for host access until the current host
access is complete. Therefore, it is essential to determine when the host access is complete
before issuing a new DCR command. While some commands complete within one clock
cycle on the DCR bus, others such as MDIO accesses require multiple clock cycles.
There are two ways to use the DCR bus with the host processor. The user can select either
polling or interrupts as a method of informing the host processor of access status. The
interrupt method is more efficient as it frees the processor to operate while waiting for the
DCR transaction to finish.
Interrupt request informs the host processor when the host interface completes a DCR
host access command. The interrupt request signal, DCRHOSTDONEIR, is only active
when the DCR bus is used, and the host interface register IRENABLE_e# is
programmed to enable interrupt. This signal is active High and level sensitive. When
a host access through the DCR bus is completed, the DCRHOSTDONEIR signal is
asserted. The host processor needs to service the interrupt request and clear the host
interface register (IRSTATUS_e#) to deassert this signal. See “DCR Interrupts” for a
description of the DCR Interrupts.
Polling of the DCR status register RDYstatus_e#. The processor polls this register to
determine access completion status. The bits in this register are asserted when there is
no access in progress. When an access is in progress, a bit corresponding to the type of
access is automatically deasserted. This bit is automatically reasserted when the
access is complete. RDYstatus_e#[15] is asserted only when there are no DCR
transactions in progress, allowing the polling process to check this one bit for all
transaction types, across both EMACs.
The DCRHOSTDONEIR interrupt can be used to manage processor DCR access. The
operation and status of the interrupt can be accessed through the IRSTATUS_e# and
IRENABLE_e# registers.
The IRSTATUS_e# register indicates which transaction type has triggered the interrupt.
This allows the host to read this register to determine the type of host access completed.
TEMAC User Guide www.xilinx.com 107
UG194 (v1.10) February 14, 2011
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