Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 2: Ethernet MAC Overview Table 2-18: Physical Interface Attributes Attribute Type Description EMAC#_CONFIGVEC_79 Boolean Reserved, set to TRUE. Attributes to Configure Default Register Values for SGMII or 1000BASE-X Management Registers The following attributes are only used in SGMII or 1000BASE- X modes. See “1000BASE-X PCS/PMA Management Registers,” page 122 and “SGMII Management Registers,” page 130 for register details. See “MDIO Implementation in the Ethernet MAC,” page 119 for information on how to access these registers. EMAC#_PHYRESET Boolean This attribute sets the default value of the Reset bit in the PCS/PMA Management Register 0 (Control Register). A value of TRUE resets the PCS/PMA module. EMAC#_PHYINITAUTONEG_ENABLE Boolean This attribute sets the default value of the Auto-Negotiation Enable bit in the PCS/PMA Management Register 0 (Control Register). A value of TRUE enables auto-negotiation of the PCS/PMA module. EMAC#_PHYISOLATE Boolean This attribute sets the default value of the Isolate bit in the PCS/PMA Management Register 0 (Control Register). A value of TRUE causes the PCS/PMA sublayer logic to behave as if it is electrically isolated from the attached Ethernet MAC, as defined in IEEE Std 802.3, clause 22.2.4.1.6. Therefore, frames transmitted by the Ethernet MAC are not forwarded through the PCS/PMA. Frames received by the PCS/PMA are not relayed to the Ethernet MAC. EMAC#_PHYPOWERDOWN Boolean This attribute sets the default value of the Power Down bit in the PCS/PMA Management Register 0 (Control Register). A value of TRUE causes the RocketIO serial transceiver to be placed in a Low power state. A reset must be applied to clear the Low power state. EMAC#_PHYLOOPBACKMSB Boolean This attribute sets the default value of the Loopback bit in the PCS/PMA Management Register 0 (Control Register). A value of TRUE for this attribute enables loopback. EMAC#_GTLOOPBACK sets if the loopback occurs in the Ethernet MAC or in the RocketIO serial transceiver. EMAC#_UNIDIRECTION_ENABLE Boolean This attribute sets the default value of the unidirection enable bit in the PCS/PMA Management Register 0 (Control Register). Setting this attribute to TRUE allows the Ethernet MAC to transmit regardless of whether a valid link has been established. EMAC#_GTLOOPBACK Boolean This attribute sets the default value of the GT Loopback bit in “Vendor-Specific Register: Loopback Control Register (Register 17),” page 129. This attribute controls where the loopback happens when loopback is selected. When EMAC#_GTLOOPBACK is TRUE, the loopback occurs in the RocketIO serial transceiver. Near-End parallel PCS loopback is used. When EMAC#_GTLOOPBACK is FALSE, the loopback is internal to the EMAC. In this state, idles are transmitted to the RocketIO serial transceiver. 48 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Table 2-18: Physical Interface Attributes (Cont’d) Attribute Type Description Ethernet MAC Attributes Attribute to Configure Auto-negotiation Parameters See the following sections for details on attribute value settings for Physical interface settings of SGMII or 1000BASE- X: SGMII: “Auto-Negotiation Link Timer,” page 197. 1000BASE-X: “Auto-Negotiation Link Timer,” page 175. EMAC#_LINKTIMERVAL[8:0] 9-bit Binary Table 2-19: Address Filter Attributes Programmable auto-negotiation link timer value. Attribute Type Description Attribute to Configure Default Register Value for the Unicast Address Register EMAC#_UNICASTADDR[47:0] 48-bit Binary Table 2-20: DCR Base Address Attributes This attribute sets the default value of the Unicast Address[47:0] in the Unicast Address (Word 0) and (Word 1) registers. See “Unicast Address (Word 0),” page 95 and “Unicast Address (Word 1),” page 95 for register details. This 48-bit attribute is used to set the Ethernet MAC unicast address used by the address filter block to see if the incoming frame is destined for the Ethernet MAC. The address is ordered for the least significant byte in the register to have the first byte transmitted or received; for example, an Ethernet MAC address of 06-05-04-03-02-01 is stored in bits [47:0] as 0x010203040506. This default value for the unicast address can be overridden by software through the host interface. Attribute Type Description Attribute to Configure Default Value for DCR Base Address EMAC#_DCRBASEADDR[7:0] 8-bit Binary See “Using the DCR Bus,” page 101 for a description of how the DCR Base Addresses are used to access different registers. This attribute allows separate DCR base addresses to be used for each Ethernet MAC. TEMAC User Guide www.xilinx.com 49 UG194 (v1.10) February 14, 2011
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47: R Table 2-17: MAC Configuration Att
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102:
R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
Page 127 and 128:
R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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Page 165 and 166:
FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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Page 187 and 188:
Page 189 and 190:
R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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Page 195 and 196:
DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 197 and 198:
Page 199 and 200:
R Interfacing to a Statistics Block
Page 201 and 202:
R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
Page 205 and 206:
R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
Page 209 and 210:
R Clock Enables Clock Connections t
Page 211 and 212:
R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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